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參數(shù)資料
| 型號： | K4M64163PK-BE900 |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| 封裝： | LEAD FREE, FBGA-54 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 114K |
| 代理商： | K4M64163PK-BE900 |
K4M64163PK - R(B)E/G/C/F
October 2005
7
Mobile-SDRAM
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next
higher integer.
2. Minimum delay is required to complete write.
3. Maximum burst refresh cycle : 8
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Parameter
Symbol
Version
Unit
Note
-75
-90
-1L
Row active to row active delay
tRRD(min)
15
18
ns
1
RAS to CAS delay
tRCD(min)
22.5
24
27
ns
1
Row precharge time
tRP(min)
22.5
24
27
ns
1
Row active time
tRAS(min)
50
ns
1
tRAS(max)
100
us
Row cycle time
tRC(min)
72.5
74
77
ns
1
Last data in to row precharge
tRDL(min)
15
ns
2
Last data in to Active delay
tDAL(min)
tRDL + tRP
-
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Auto refresh cycle time
tARFC(min)
80
ns
3
Exit self refresh to active command
tSRFX(min)
120
ns
Col. address to col. address delay
tCCD(min)
1
CLK
4
Number of valid output data
CAS latency=3
2
ea
5
Number of valid output data
CAS latency=2
1
Number of valid output data
CAS latency=1
-
0
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