
K4S161622E
CMOS SDRAM
Rev 1.1 Jan '03
The K4S161622E is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with SAMSUNG
′
s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
3.3V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-. CAS Latency ( 2 & 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
15.6us refresh duty cycle (2K/32ms)
GENERAL DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
512K x 16Bit x 2 Banks Synchronous DRAM
ORDERING INFORMATION
Part NO.
MAX Freq.
183MHz
166MHz
143MHz
125MHz
100MHz
Interface Package
K4S161622E-TC55
K4S161622E-TC60
K4S161622E-TC70
K4S161622E-TC80
K4S161622E-TC10
LVTTL
50
TSOP(II)
* Samsung Electronics reserves the right to change products or specification without notice.
Bank Select
Data Input Register
512K x 16
512K x 16
S
O
I
Column Decoder
Latency & Burst Length
Programming Register
A
R
R
R
C
L
L
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
Timing Register