參數(shù)資料
型號(hào): K6T1008C2C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 128K x8 bit Low Power CMOS Static RAM
中文描述: 128K的x8位低功耗CMOS靜態(tài)RAM
文件頁(yè)數(shù): 6/10頁(yè)
文件大?。?/td> 189K
代理商: K6T1008C2C
PRELIMINARY
K6T1008C2C Family
CMOS SRAM
Revision 2.0
November 1997
5
CL
1)
1. Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :CL=100pF+1TTL
AC CHARACTERISTICS
Parameter List
Symbol
Speed Bins
Units
55ns
70ns
Min
Max
Min
Max
Read
Read cycle time
tRC
55
-
70
-
ns
Address access time
tAA
-
55
-
70
ns
Chip select to output
tCO1, tCO2
-
55
-
70
ns
Output enable to valid output
tOE
-
25
-
35
ns
Chip select to low-Z output
tLZ
10
-
10
-
ns
Output enable to low-Z output
tOLZ
5
-
5
-
ns
Chip disable to high-Z output
tHZ
0
20
0
25
ns
Output disable to high-Z output
tOHZ
0
20
0
25
ns
Output hold from address change
tOH
10
-
10
-
ns
Write
Write cycle time
tWC
55
-
70
-
ns
Chip select to end of write
tCW
45
-
60
-
ns
Address set-up time
tAS
0
-
0
-
ns
Address valid to end of write
tAW
45
-
60
-
ns
Write pulse width
tWP
40
-
50
-
ns
Write recovery time
tWR1,tWR2
0
-
0
-
ns
Write to output high-Z
tWHZ
0
20
0
25
ns
Data to write time overlap
tDW
25
-
30
-
ns
Data hold from write time
tDH
0
-
0
-
ns
End write to output low-Z
tOW
5
-
5
-
ns
DATA RETENTION CHARACTERISTICS
1. CS1
≥Vcc-0.2v, CS2≥Vcc-0.2V or CS2≤0.2V
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
VDR
CS11)
≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V
2.0
-
5.5
V
Data retention current
IDR
Vcc=3.0V, CS1
≥Vcc-0.2V,
CS2
≥Vcc-0.2V or CS2≤0.2V
K6T1008C2C-L
-
1
20
A
K6T1008C2C-B
-
1
10
K6T1008C2C-P
-
25
K6T1008C2C-F
-
10
Data retention set-up
tSDR
See data retention waveform
0
-
ms
Recovery time
tRDR
5
-
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