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參數(shù)資料
| 型號： | K7N323601M-QC25 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Mx36 & 2Mx18 Flow-Through NtRAM |
| 中文描述： | 1Mx36 |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 211K |
| 代理商： | K7N323601M-QC25 |
1Mx36 & 2Mx18 Flow-Through N
t
RAM
TM
- 5 -
Rev 2.0
Nov. 2003
K7M321825M
K7M323625M
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
N.C.
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
N.C.
DQb
8
DQb
7
V
SSQ
V
DDQ
DQb
6
DQb
5
V
SS
V
DD
V
DD
V
SS
DQb
4
DQb
3
V
DDQ
V
SSQ
DQb
2
DQb
1
DQb
0
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
10
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
DQa
0
DQa
1
DQa
2
V
SSQ
V
DDQ
DQa
3
DQa
4
V
SS
V
SS
V
DD
ZZ
DQa
5
DQa
6
V
DDQ
V
SSQ
DQa
7
DQa
8
N.C.
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
1
9
9
9
9
9
9
9
9
9
9
8
8
8
8
8
8
8
8
A
6
A
7
C
1
C
2
B
B
C
2
V
D
V
S
C
W
C
O
A
A
1
A
1
A
8
8
A
9
5
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
A
1
A
1
A
1
A
1
A
1
A
1
A
1
A
2
N
V
D
V
S
N
N
A
0
A
1
A
2
A
3
A
4
A
5
3
L
K7M321825M(2Mx18)
N
N
PIN NAME
Notes :
1. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A
0
- A
20
ADV
WE
CLK
CKE
CS
1
CS
2
CS
2
BWx(x=a,b)
OE
ZZ
LBO
Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
32,33,34,35,36,37,43
44,45,46,47,48,49,50,
80,81,82,83,84,99,100
85
88
89
87
98
97
92
93,94
86
64
31
V
DD
V
SS
N.C.
DQa
0
~a
8
DQb
0
~b
8
V
DDQ
V
SSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Output Power Supply
(2.5V or 3.3V)
Output Ground
15,16,41,65,91
14,17,40,66,67,90
1,2,3,6,7,25,28,29,30,
38,39,42,51,52,53,
56,57,75,78,79,95,96
58,59,62,63,68,69,72,73,74
8,9,12,13,18,19,22,23,24
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
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