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參數(shù)資料
| 型號： | K7N323645M-QC20 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Mx36 & 2Mx18 Flow-Through NtRAM |
| 中文描述： | 1Mx36 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大小： | 211K |
| 代理商： | K7N323645M-QC20 |
1Mx36 & 2Mx18 Flow-Through N
t
RAM
TM
- 3 -
Rev 2.0
Nov. 2003
K7M321825M
K7M323625M
1Mx36 & 2Mx18-Bit Flow Through N
t
RAM
TM
The K7M323625M and K7M321825M are 37,748,736-bits Syn-
chronous Static SRAMs.
The N
t
RAM
TM
, or No Turnaround Random Access Memory uti-
lizes all bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, Flow-Through SRAM allows output data to
simply flow freely from the memory array.
The K7M323625M and K7M321825M are implemented with
SAMSUNG
′
s high performance CMOS technology and is avail-
able in 100pin TQFP packages. Multiple power and ground pins
minimize ground bounce.
GENERAL DESCRIPTION
FEATURES
3.3V+0.165V/-0.165V Power Supply.
I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
Byte Writable Function.
Enable clock and suspend operation.
Single READ/WRITE control pin.
Self-Timed Write Cycle.
Three Chip Enable for simple depth expansion with no data
contention .
A interleaved burst or a linear burst mode.
Asynchronous output enable control.
Power Down mode.
TTL-Level Three-State Outputs.
100-TQFP-1420A .
LOGIC BLOCK DIAGRAM
N
t
RAM
TM
and No Turnaround Random Access Memory are trademarks of Samsung.
WE
BW
(x=a,b,c,d or a,b)
CLK
CKE
CS
1
CS
2
CS
2
ADV
OE
ZZ
DQa
~ DQd
7
or
DQa
0
~ DQb
8
DQPa ~ DQPd
ADDRESS
REGISTER
ADDRESS
REGISTER
C
L
A
′
0
~A
′
1
36 or 18
BUFFER
DATA-IN
REGISTER
K
BURST
ADDRESS
COUNTER
WRITE
CONTROL
LOGIC
C
R
K
A [0:19]or
A [0:20]
LBO
A
0
~A
1
A
2
~A
19
or
A
2
~A
20
1Mx36 , 2Mx18
MEMORY
ARRAY
FAST ACCESS TIMES
Parameter
Symbol
-75
Unit
Cycle Time
t
CYC
8.5
ns
Clock Access Time
t
CD
7.5
ns
Output Enable Access Time
t
OE
3.5
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K7N323645M-QC25 | 1Mx36 & 2Mx18 Flow-Through NtRAM |
| K7M321825M | 1Mx36 & 2Mx18 Flow-Through NtRAM |
| K7N321801M | 1Mx36 & 2Mx18-Bit Pipelined NtRAM |
| K7N323601M | 1Mx36 & 2Mx18-Bit Pipelined NtRAM |
| K7N401801A | 128Kx36 & 256Kx18-Bit Pipelined NtRAMTM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7N323645M-QC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx36 & 2Mx18 Flow-Through NtRAM |
| K7N401801A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18-Bit Pipelined NtRAMTM |
| K7N401801A-QC13 | 制造商:Samsung Semiconductor 功能描述: |
| K7N401801A-QC15000 | 制造商:Samsung SDI 功能描述:S5 |
| K7N401801B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18 Pipelined NtRAM |
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