參數(shù)資料
型號: K9D1G08V0M
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 64MB & 128MB SmartMediaTM Card
中文描述: 64MB的
文件頁數(shù): 7/37頁
文件大小: 657K
代理商: K9D1G08V0M
SmartMedia
TM
7
K9S1208V0M/A-SSB0
K9D1G08V0M/A-SSB0
Product Introduction
The SmartMeida has the memory organization as following Table1. Spare sixteen columns are located from column address of 512 to
527. A 528-byte data register is connected to memory cell arrays and is accommodating data-transfer between the I/O buffers and
memory cell arrays during page read and page program operations. The memory array is made up of 16 cells that are serially con-
nected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages formed by two 16
cell memory array. The array organization is shown in Figure 2. The program and the read operations are executed on a page basis,
while the erase operation is executed on a block basis.
The SmartMedia has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows system upgrade to
future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 128M byte and 64M byte physical space
requires 26 and 25 addresses, thereby requiring four cycles for byte-level addressing; column address, row address, in that order.
Page Read and Page Program need the same four address cycles following the required command input. In Block Erase operation,
however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command
register. Table 2 defines the specific commands of the SmarMedia.
The device provides simultaneous program/erase capability up to four pages/blocks. By dividing the memory array into eight 128Mbit
separate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4X while still maintaining
the conventional 512 byte structure.
The extended pass/fail status for multi-plane program/erase allows system software to quickly identify the failing page/block out of
selected multiple pages/blocks. Usage of multi-plane operations will be described further throughout this document.
Table2. Command Sets
NOTE
: 1. The 00h command defines starting address of the 1st half of registers.The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the address pointer is automatically moved to the 1st half register(00h) on
the next cycle.
2. Any undefind commands are prohibited, which are not mentioned above command set table.
Function
1st. Cycle
2nd. Cycle
3rd. Cycle
Acceptable Command during
Read 1
00h/01h
(1)
-
-
Read 2
50h
-
-
Read ID
90h
-
-
Reset
FFh
-
-
O
Page Program (True)
80h
10h
-
Page Program (Dummy)
80h
11h
-
Page Program (Multi Block Program)
80h
15h
-
Block Erase
60h
D0h
-
Multi-Plane Block Erase
60h---60h
D0h
-
Read Status
70h
-
-
O
Read Multi-Plane Status
71h
(2)
-
-
O
Table 1. MEMORY ORGANIZATION
Memory Organization
Number of rows(Pages)
Number of columns
K9S1208V0X
528Mbit
(553,648,218 bit)
131,072 rows
528 columns
K9D1G08V0X
1,056M bit
(1,107,296,436 bit)
262,144 rows
528 columns
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