參數(shù)資料
型號: K9F1G08D0M
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
元件分類: 圓形連接器
英文描述: Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TV07; Number of Contacts:37; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Jam Nut Receptacle; Body Style:Straight
中文描述: 128M的× 8位/ 64米× 16位NAND閃存
文件頁數(shù): 12/40頁
文件大?。?/td> 729K
代理商: K9F1G08D0M
FLASH MEMORY
12
K9F1G08D0M
K9F1G08U0M
K9F1G16Q0M
K9F1G16D0M
K9F1G16U0M
K9F1G08Q0M
CAPACITANCE
(
T
A
=25
°
C, V
CC
=1.8V/2.65V/3.3V, f=1.0MHz)
NOTE
: Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
C
I/O
V
IL
=0V
-
10
pF
Input Capacitance
C
IN
V
IN
=0V
-
10
pF
VALID BLOCK
NOTE
:
1. The
K9F1GXXX0M
may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase
or program factory-marked bad blocks
.
Refer to the attached technical notes for appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase
cycles.
AC TEST CONDITION
(K9F1GXXX0M-XCB0 :TA=0 to 70
°
C, K9F1GXXX0M-XIB0:TA=-40 to 85
°
C
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
N
VB
1004
-
1024
Blocks
K9F1GXXQ0M : Vcc=1.70V~1.95V, K9F1GXXD0M : Vcc=2.4V~2.9V , K9F1GXXU0M : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9F1GXXQ0M
K9F1GXXD0M
K9F1GXXU0M
Input Pulse Levels
0V to Vcc
0V to Vcc
0.4V to 2.4V
Input Rise and Fall Times
5ns
5ns
5ns
Input and Output Timing Levels
Vcc/2
Vcc/2
1.5V
K9F1GXXQ0M:Output Load (Vcc:1.8V +/-10%)
K9F1GXXD0M:Output Load (Vcc
Q
:2.65V +/-10%)
K9F1GXXU0M:Output Load (Vcc:3.0V +/-10%)
1 TTL GATE and CL=30pF1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF
K9F1GXXU0M:Output Load (Vcc:3.3V +/-10%)
-
-
1 TTL GATE and CL=100pF
MODE SELECTION
NOTE
: 1. X can be V
IL
or V
IH.
2. WP and PRE should be biased to CMOS high or CMOS low for standby.
CLE
ALE
CE
WE
RE
WP
PRE
Mode
H
L
L
H
X
X
Read Mode Command Input
Address Input(4clock)
L
H
L
H
X
X
H
L
L
H
H
X
Write Mode Command Input
Address Input(4clock)
L
H
L
H
H
X
L
L
L
H
H
X
Data Input
L
L
L
H
X
X
Data Output
X
X
X
X
H
X
X
During Read(Busy)
X
X
X
X
X
H
X
During Program(Busy)
X
X
X
X
X
H
X
During Erase(Busy)
X
X
(1)
X
X
X
L
X
Write Protect
X
X
H
X
X
0V/V
CC
(2)
0V/V
CC
(2)
Stand-by
相關(guān)PDF資料
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