參數(shù)資料
          型號(hào): K9F5608U0C-P
          廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
          英文描述: 512Mb/256Mb 1.8V NAND Flash Errata
          中文描述: 512Mb/256Mb 1.8 NAND閃存勘誤表
          文件頁(yè)數(shù): 7/39頁(yè)
          文件大小: 655K
          代理商: K9F5608U0C-P
          K9F5616U0C-YCB0,YIB0,PCB0,PIB0
          K9F5616U0C-DCB0,DIB0,HCB0,HIB0
          FLASH MEMORY
          6
          K9F5608U0C-YCB0,YIB0,PCB0,PIB0
          K9F5608U0C-DCB0,DIB0,HCB0,HIB0
          K9F5608Q0C-DCB0,DIB0,HCB0,HIB0
          K9F5616Q0C-DCB0,DIB0,HCB0,HIB0
          K9F5608U0C-VCB0,VIB0,FCB0,FIB0
          PIN DESCRIPTION
          Pin NAME
          Pin Function
          I/O
          0
          ~ I/O
          7
          (K9F5608X0C)
          I/O
          0
          ~ I/O
          15
          (K9F5616X0C)
          DATA INPUTS/OUTPUTS
          The I/O pins are used to input command, address and data, and to output data during read operations. The
          I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
          I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-
          ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
          output.
          CLE
          COMMAND LATCH ENABLE
          The CLE input controls the activating path for commands sent to the command register. When active high,
          commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
          ALE
          ADDRESS LATCH ENABLE
          The ALE input controls the activating path for address to the internal address registers. Addresses are
          latched on the rising edge of WE with ALE high.
          CE
          CHIP ENABLE
          The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
          the device does not return to standby mode in program or erase opertion. Regarding CE control during read
          operation, refer to ’Page read’ section of Device operation .
          RE
          READ ENABLE
          The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
          tREA after the falling edge of RE which also increments the internal column address counter by one.
          WE
          WRITE ENABLE
          The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
          the WE pulse.
          WP
          WRITE PROTECT
          The WP pin provides inadvertent write/erase protection during power tra nsitions. The internal high voltage
          generator is reset when the WP pin is active low. When LOCKPRE is a logic high and WP is a logic low, the
          all blocks go to lock state.
          R/B
          READY/BUSY OUTPUT
          The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
          random read operation is in process and returns to high state upon completion. It is an open drain output and
          does not float to high-z condition when the chip is deselected or when outputs are disabled.
          VccQ
          OUTPUT BUFFER POWER
          V
          CC
          Q is the power supply for Output Buffer.
          VccQ is internally connected to Vcc, thus should be biased to Vcc.
          Vcc
          POWER
          V
          CC
          is the power supply for device.
          Vss
          GROUND
          N.C
          NO CONNECTION
          Lead is not internally connected.
          DNU
          DO NOT USE
          Leave it disconnected
          LOCKPRE
          LOCK MECHANISM & POWER-ON AUTO-READ ENABLE
          To Enable and disable the Lock mechanism and Power On Auto Read. When LOCKPRE is a logic high,
          Block Lock mode and Power-On Auto-Read mode are enabled, and when LOCKPRE is a logic low, Block
          Lock mode and Power-On Auto-Read mode are disabled. Power-On Auto-Read mode is available only on
          3.3V device(K9F56XXU0C)
          Don’t leave it N.C
          .
          Not using
          LOCK MECHANISM & POWER-ON AUTO-READ, connect it Vss.
          NOTE
          : Connect all V
          CC
          and V
          SS
          pins of each device to common power supply outputs.
          Do not leave V
          CC
          or V
          SS
          disconnected.
          相關(guān)PDF資料
          PDF描述
          K9F5608U0C-V 512Mb/256Mb 1.8V NAND Flash Errata
          K9F5608U0C-Y 512Mb/256Mb 1.8V NAND Flash Errata
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          K9F5616Q0C-D 512Mb/256Mb 1.8V NAND Flash Errata
          K9F5616Q0C-H 512Mb/256Mb 1.8V NAND Flash Errata
          相關(guān)代理商/技術(shù)參數(shù)
          參數(shù)描述
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          K9F5608U0C-VCB0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mb/256Mb 1.8V NAND Flash Errata