![](http://datasheet.mmic.net.cn/300000/K9K1208D0C_datasheet_16195998/K9K1208D0C_11.png)
FLASH MEMORY
11
K9K1216D0C
K9K1216U0C
K9K1208U0C
K9K1208Q0C
K9K1216Q0C
CAPACITANCE
(
T
A
=25
°
C, V
CC
=1.8V/2.65V/3.3V, f=1.0MHz)
NOTE
: Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
C
I/O
V
IL
=0V
-
20
pF
Input Capacitance
C
IN
V
IN
=0V
-
20
pF
VALID BLOCK
NOTE
:
1. The
device
may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits
.
Do not erase or program
factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase
cycles.
3. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
N
VB
4026
-
4096
Blocks
AC TEST CONDITION
(K9K12XXX0C-GCB0,JCB0 :TA=0 to 70
°
C, K9K12XXX0C-GIB0,JCB0 :TA=-40 to 85
°
C
K9K12XXQ0C : Vcc=1.70V~1.95V , K9K12XXD0C : Vcc=2.4V~2.9V , K9K12XXU0C : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9K12XXQ0C
K9K12XXD0C
K9K12XXU0C
Input Pulse Levels
0V to Vcc
Q
0V to Vcc
Q
0.4V to 2.4V
Input Rise and Fall Times
5ns
5ns
5ns
Input and Output Timing Levels
Vcc
Q
/2
Vcc
Q
/2
1.5V
K9K12XXQ0C:Output Load (Vcc
Q
:1.8V +/-10%)
K9K12XXD0C:Output Load (Vcc
Q
:2.65V +/-10%)
K9K12XXU0C:Output Load (Vcc
Q
:3.0V +/-10%)
1 TTL GATE and CL=30pF1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF
K9K12XXU0C:Output Load (Vcc
Q
:3.3V +/-10%)
-
-
1 TTL GATE and CL=100pF
MODE SELECTION
NOTE
: 1. X can be V
IL
or V
IH.
2. WP should be biased to CMOS high or CMOS low for standby.
CLE
ALE
CE
WE
RE
LOCKPRE
WP
Mode
H
L
L
H
X
X
Read Mode
Command Input
L
H
L
H
X
X
Address Input(4clock)
H
L
L
H
X
H
Write Mode
Command Input
L
H
L
H
X
H
Address Input(4clock)
L
L
L
H
X
H
Data Input
L
L
L
H
X
X
Data Output
X
X
X
X
H
X
X
During Read(Busy) on the devices
X
X
X
X
X
X
H
During Program(Busy)
X
X
X
X
X
X
H
During Erase(Busy)
X
X
(1)
X
X
X
X
L
Write Protect
X
X
H
X
X
0V/V
CC
(2
0V/V
CC
(2)
Stand-by