參數(shù)資料
型號(hào)： KAD5510P-50Q72
廠商： Intersil
文件頁(yè)數(shù)： 8/29頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT 500MSPS SGL 72-QFN
產(chǎn)品培訓(xùn)模塊： High-Speed Analog-to-Digital Converters
標(biāo)準(zhǔn)包裝： 1
系列： FemtoCharge™
位數(shù)： 10
采樣率（每秒）： 500M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 438mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 72-QFN（10x10）
包裝： 托盤
輸入數(shù)目和類型： 1 個(gè)差分，單極
16
FN6811.2
October 8, 2009
Best performance is obtained when the analog inputs are
driven differentially. The common-mode output voltage,
VCM, should be used to properly bias the inputs as shown in
Figures 26 through 28. An RF transformer will give the best
noise and distortion performance for wideband and/or high
intermediate frequency (IF) inputs. Two different transformer
input schemes are shown in Figures 26 and 27.
This dual transformer scheme is used to improve
common-mode rejection, which keeps the common-mode
level of the input matched to VCM. The value of the shunt
resistor should be determined based on the desired load
impedance. The differential input resistance of the
KAD5510P-50 is 500
Ω.
The SHA design uses a switched capacitor input stage
(see Figure 41), which creates current spikes when the
sampling capacitance is reconnected to the input voltage.
This causes a disturbance at the input which must settle
before the next sampling point. Lower source impedance will
result in faster settling and improved performance. Therefore
a 1:1 transformer and low shunt resistance are
recommended for optimal performance.
A differential amplifier, as shown in Figure 28, can be used in
applications that require DC-coupling. In this configuration
the amplifier will typically dominate the achievable SNR and
distortion performance.
Clock Input
The clock input circuit is a differential pair (see Figure 42).
Driving these inputs with a high level (up to 1.8VP-P on each
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels.
The recommended drive circuit is shown in Figure 29. A
duty range of 40% to 60% is acceptable. The clock can be
driven single-ended, but this will reduce the edge rate and
may impact SNR performance. The clock inputs are
internally self-biased to AVDD/2 to facilitate AC-coupling.
A selectable 2x frequency divider is provided in series with
the clock input. The divider can be used in the 2x mode with
a sample clock equal to twice the desired sample rate. This
allows the use of the Phase Slip feature, which enables
synchronization of multiple ADCs.
The clock divider can also be controlled through the SPI
port, which overrides the CLKDIV pin setting. Details on this
FIGURE 25. ANALOG INPUT RANGE
1.0
1.8
0.6
0.2
1.4
INP
INN
VCM
0.535V
0.725V
FIGURE 26. TRANSFORMER INPUT FOR GENERAL
PURPOSE APPLICATIONS
ADT1-1WT
0.1F
KAD5510P-50
VCM
ADT1-1WT
1000pF
FIGURE 27. TRANSMISSION-LINE TRANSFORMER INPUT
FOR HIGH IF APPLICATIONS
ADTL1-12
0.1F
KAD5510P-50
VCM
ADTL1-12
1000pF
TABLE 1. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
Float
1
AVDD
Not Allowed
FIGURE 28. DIFFERENTIAL AMPLIFIER INPUT
KAD5510P-50
VCM
0.1F
0.22F
69.8O
49.9O
100O
69.8O
348O
CM
217O
25O
Ω
FIGURE 29. RECOMMENDED CLOCK DRIVE
TC4-1W
200pF
AVDD
200O
200pF
CLKP
CLKN
1kO
1000pF
Ω
KAD5510P-50
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