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參數(shù)資料
| 型號(hào)： | KFH4G16D2M-DID5 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | FLASH MEMORY(54MHz) |
| 中文描述： | 閃存（54MHz之間） |
| 文件頁(yè)數(shù)： | 83/125頁(yè) |
| 文件大?。?/td> | 1657K |
| 代理商： | KFH4G16D2M-DID5 |
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OneNAND1G(KFG1G16Q2M-DEB5)
FLASH MEMORY
83
OneNAND2G(KFH2G16Q2M-DEB5)
OneNAND4G(KFW4G16Q2M-DEB5)
In order to perform the Internal Erase Routine, the following command sequence is necessary.
The Host selects Flash Core of DDP chip.
The Host sets the block address of the memory location.
The Erase Command initiates the Internal Erase Routine. During the execution of the Routine, the host is
not required to provide further controls or timings. During the Internal erase routine, all commands, except
the Reset command and Erase Suspend Command, written to the device will be ignored.
A reset during an erase operation will cause data corruption at the corresponding location.
Using Multi-Block Erase, the device can erase up to 64 multiple blocks simultaneously.
Multiple blocks can be erased by issuing a Multi-Block Erase command and writing the block address of the memory location to be
erased. The final Flash Block Address (FBA) and Block Erase command initiate the internal multi block erase routine. During a
Multi-Block Erase, the OnGo bit of the Controller Status Register is set to '1'(busy) from the time first block address to be latched is
written until the actual erase has finished.
During block address latch sequence, issuing of other commands except Block Erase and Multi Block Erase at INT=High will abort
the current operation. So to speak, It will cancel the previously latched addresses of Multi Block Erase Operation.
On the other hand, Other command issue at INT=low will be ignored.
A reset during an erase operation will cause data corruption at the address location being operated on during the reset.
Despite a failed block during Multi-Block Erase operation, the device will continue the erase operation until all other specified blocks
are erased.
Erase Suspend Command issue during Multi Block Erase Address latch sequence is prohibited.
Locked Blocks
If there are locked blocks in the specified range, the Multi-Block Erase operation works as the follows.
Case 1: All specified blocks except BA(2) will be erased.
[BA(1)+0095h] + [
BA((2), locked))
+0095h] + ... + [BA(N-1)+0095h] + [BA(N)+0094h]
Case 2: Multi-Block Erase Operation is suspended and fails to start if the last Block Erase command is put together with the locked
block address until right command and address input are issued.
[BA(1)+0095h] + [BA(2)+0095h] + ... + [BA(N-1)+0095h] + [
BA((N), locked))
+0094h]
Case 3: All specified blocks except BA(N) are erased.
[BA(1)+0095h] + [BA(2)+0095h] + ... + [BA(N-1)+0095h] + [
BA((N, locked))
+0094h] + [BA(N+1)+0094h]
3.10.2 Multi-Block Erase Operation
See Timing Diagram 6.10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KFH4G16D2M-DID6 | FLASH MEMORY(54MHz) |
| KFH4G16Q2M-DED5 | FLASH MEMORY(54MHz) |
| KFH4G16Q2M-DED6 | FLASH MEMORY(54MHz) |
| KFH4G16Q2M-DIB6 | FLASH MEMORY(54MHz) |
| KFH4G16Q2M-DID5 | FLASH MEMORY(54MHz) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KFH4G16D2M-DID6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY(54MHz) |
| KFH4G16Q2M-DEB5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY(54MHz) |
| KFH4G16Q2M-DEB6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY(54MHz) |
| KFH4G16Q2M-DEB8000 | 制造商:Samsung Semiconductor 功能描述:4GNOFLASHDX1663 FBGA (10X13) - Bulk |
| KFH4G16Q2M-DED5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY(54MHz) |
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