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參數(shù)資料
| 型號： | KIT33975AEWEVBE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 8/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVALUATION FOR MC33975 |
| 標準包裝： | 1 |
| 主要目的： | 接口，開關(guān)探測 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | MC33975 |
| 主要屬性： | 8 可編程輸入（電池開關(guān)或接地開關(guān)） |
| 次要屬性： | 14 開關(guān)至接地輸入 |
| 已供物品： | 板，CD |
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Analog Integrated Circuit Device Data
16
Freescale Semiconductor
33975
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
POWER SUPPLY
The 33975 is designed to operate from 5.5 to 38/40 V on the
VPWR pin. Characteristics are provided from 8.0 to 28 V for
the device. Switch contact currents and the internal logic
supply are generated from the VPWR pin. The VDD supply
pin is used to set the SPI communication voltage levels,
current source for the SO driver, and pull-up current on INT
and CS.
VDD supply may be removed from the device to reduce
quiescent current. If VDD is removed while the device is in
Normal mode, the device will remain in Normal mode. If VDD
is removed in Sleep mode, the device will remain in Sleep
mode until a wake-up input is received (WAKE high to low,
switch input or interrupt timer expires).
Removing VDD from the device disables SPI communication
and will not allow the device to wake up from the INT and CS
pins.
POWER-ON RESET (POR)
Applying VPWR to the device will cause a Power-ON Reset
and place the device in Normal mode.
Default settings from Power-ON Reset via a VPWR or Reset
Command are as follows:
Programmable switch – Set to switch-to-battery
All inputs set as wake-up
Wetting current on (16 mA pull-down, 32 mA pull-up)
Wetting current timer on (20 ms)
All inputs tri-state
Analog select 00000 (no input channel selected)
Note The 33975 device provides indication that a reset has
occurred by placing a logic [1] in bit 22 of the SO buffer. The
reset bit is cleared on rising edge of CS.
OPERATIONAL MODES
The 33975 has two operating modes, Normal mode and
Sleep mode. A discussion on Normal mode begins below. A
discussion on Sleep Mode begins on page 21.
NORMAL MODE
Normal mode may be entered by the following events:
Application of VPWR to the IC
Change-of-switch state (when enabled)
Falling edge of WAKE
Falling edge of INT (with VDD = 5.0 V and WAKE at
Logic [1])
Falling edge of CS (with VDD = 5.0 V)
Interrupt timer expires
Only in Normal mode with VDD applied can the registers of
the 33975 be programmed through the SPI.
The registers that may be programmed in Normal mode are
listed below. Further explanation of each register is provided
in subsequent paragraphs.
Programmable Switch Register (Settings Command)
Wake-up/Interrupt Register (Wake-up/Interrupt
Command)
Wetting Current Register (Metallic Command)
Wetting Current Timer Register (Wetting Current Timer
Enable Command)
Tri-state Register (Tri-state Command)
Analog Select Register (Analog Command)
Calibration of Timers (Calibration Command)
Reset (Reset Command)
Figure 6, page 11, is a graphical description of the device
operation in Normal mode. Switch states are latched into the
input register on the falling edge of CS. The INT to the MCU
is cleared on the rising edge of CS. However, INT will not
clear on the rising edge of CS if a switch has closed during
SPI communication (CS low). This prevents switch states
from being missed by the MCU.
PROGRAMMABLE SWITCH REGISTER
Inputs SP0 to SP7 may be programmable for switch-to-
battery or switch-to-ground. These inputs types are defined
using the settings command (refer to Table 6). To set an SPn
input for switch-to-battery, a logic [1] for the appropriate bit
must be set. To set an SPn input for switch-to-ground, a
logic [0] for the appropriate bit must be set. The MCU may
change or update the Programmable Switch Register via
software at any time in Normal mode. Regardless of the
setting, when the SPn input switch is closed a logic [1] will be
placed in the Serial Output Response Register (refer to
Table 6. Settings Command
Settings Command
Not used
Battery/Ground Select
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
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