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參數(shù)資料
| 型號(hào)： | KM416C1000B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 16Bit CMOS Dynamic RAM with Fast Page Mode |
| 中文描述： | 100萬(wàn)× 16的CMOS動(dòng)態(tài)隨機(jī)存儲(chǔ)器的快速頁(yè)面模式 |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大?。?/td> | 84K |
| 代理商： | KM416C1000B |
KM416C1000B, KM416C1200B
KM416V1000B, KM416V1200B
CMOS DRAM
NOTES
An initial pause of 200us is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is
achieved.
Input voltage levels are Vih/Vil. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals.
Transition times are measured between V
IH
(min) and V
IL
(max) and are assumed to be 5ns for all inputs.
Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max) can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
oh
or V
ol
.
t
WCS
,
t
RWD
,
t
CWD
,
t
AWD
and
t
CPWD
are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If
t
WCS
t
WCS
(min), the cycles is an early write cycle and the data output will remain high impedance for
the duration of the cycle. If
t
CWD
t
CWD
(min),
t
RWD
t
RWD
(min),
t
AWD
t
AWD
(min) and
t
CPWD
t
CPWD
(min), then the cycle is a
read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above condi-
tions is satisfied, the condition of the data out is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to the CAS leading edge in ealy write cycles and to the W falling edge in OE controlled write
cycle and read-modify-write cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max) can be met.
t
RAD
(max) is specified as a reference point only. If
t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is controlled by
t
AA
.
KM416C/V10(2)00B/BL Truth Table
RAS
LCAS
UCAS
W
OE
DQ0 - DQ7
DQ8-DQ15
STATE
H
X
X
X
X
Hi-Z
Hi-Z
Standby
L
H
H
X
X
Hi-Z
Hi-Z
Refresh
L
L
H
H
L
DQ-OUT
Hi-Z
Byte Read
L
H
L
H
L
Hi-Z
DQ-OUT
Byte Read
L
L
L
H
L
DQ-OUT
DQ-OUT
Word Read
L
L
H
L
H
DQ-IN
-
Byte Write
L
H
L
L
H
-
DQ-IN
Byte Write
L
L
L
L
H
DQ-IN
DQ-IN
Word Write
L
L
L
H
H
Hi-Z
Hi-Z
-
7.
6.
5.
9.
8.
3.
2.
1.
4.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KM416V1000B | 1M x 16Bit CMOS Dynamic RAM with Fast Page Mode |
| KM416V1200B | 1M x 16Bit CMOS Dynamic RAM with Fast Page Mode |
| KM416C1200C | 12.4K OHM 1% 1/2W M/F LEADED RESISTOR |
| KM416C1000C | 1M x 16Bit CMOS Dynamic RAM with Fast Page Mode |
| KM416V1000C | 1M x 16Bit CMOS Dynamic RAM with Fast Page Mode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM416C1000C | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:1M x 16Bit CMOS Dynamic RAM with Fast Page Mode |
| KM416C1004C | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:1M x 16Bit CMOS Dynamic RAM with Extended Data Out |
| KM416C1004C-45 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:1M x 16Bit CMOS Dynamic RAM with Extended Data Out |
| KM416C1004C-5 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:1M x 16Bit CMOS Dynamic RAM with Extended Data Out |
| KM416C1004C-6 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:1M x 16Bit CMOS Dynamic RAM with Extended Data Out |
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