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參數(shù)資料
| 型號： | KM416L8031BT-G(F)Z |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR SDRAM Specification Version 0.61 |
| 中文描述： | DDR SDRAM的規(guī)格版本0.61 |
| 文件頁數(shù)： | 14/53頁 |
| 文件大小： | 669K |
| 代理商： | KM416L8031BT-G(F)Z |
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- 14 -
REV. 1.0 November. 2. 2000
128Mb DDR SDRAM
3.2.1 Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE at a low state(all other inputs may be undefined.)
- Apply VDD before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & Vref.
2. Start clock and maintain stable condition for a minimum of 200us.
3. The minimum of 200us after stable power and clock(CK, CK), apply NOP & take CKE high.
4. Issue precharge commands for all banks of the device.
5. Issue EMRS to enable DLL.(To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low"
to all of the rest address pins, A1~A11 and BA1)
6. Issue a mode register set command for "DLL reset". The additional 200 cycles of clock input is required to
lock the DLL.
(To issue DLL reset command, provide "High" to A8 and "Low" to BA0)
7. Issue precharge commands for all banks of the device.
8. Issue 2 or more auto-refresh commands.
9. Issue a mode register set command with low to A8 to initialize device operation.
*1 Every "DLL enable" command resets DLL. Therefore sequence 6 can be skipped during power up.
Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6 & 7 is regardless of the order.
Power up & Initialization Sequence
Command
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
t
RP
2 Clock min.
precharge
ALL Banks
2nd Auto
Refresh
Mode
Register Set
CoAny
t
RFC
～
1st Auto
Refresh
t
RFC
min.200 Cycle
EMRS
MRS
2 Clock min.
DLL Reset
*1
*2
*1
2 Clock min.
～
～
～
～
precharge
ALL Banks
t
RP
CK
CK
3.2 Basic Functionality
Figure 4. Power up and initialization sequence
相關(guān)PDF資料 |
PDF描述 |
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| KM44L32031BT-G(L)0 | DDR SDRAM Specification Version 1.0 |
| KM48L16031BT-G(L)0 | DDR SDRAM Specification Version 1.0 |
| KM416L8031BT-G(L)0 | DDR SDRAM Specification Version 1.0 |
| KM44L32031BT-G(L)Y | DDR SDRAM Specification Version 1.0 |
| KM48S2020C | 1M x 8Bit x 2 Banks Synchronous DRAM(1M x 8位 x 2組同步動態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM416L8031BT-GFZ/Y/0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Specification Version 0.61 |
| KM416L8031BT-GLZ/Y/0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Specification Version 1.0 |
| KM416RD16AC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM416RD16AD | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM416RD16C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
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