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參數(shù)資料
| 型號： | KM44L32031BT-G(F)Y |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR SDRAM Specification Version 0.61 |
| 中文描述： | DDR SDRAM的規(guī)格版本0.61 |
| 文件頁數(shù)： | 45/53頁 |
| 文件大?。?/td> | 669K |
| 代理商： | KM44L32031BT-G(F)Y |
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- 45 -
REV. 1.0 November. 2. 2000
128Mb DDR SDRAM
Table 14. AC timing parameters and specifications
1. Maximum burst refresh of 8
2. tHZQ transitions occurs in the same access time windows as valid data transitions. These parameters are not referenced
to a specific voltage level, but specify when the device output is no longer driving.
3. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
4. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
5. The value of tQCSW min. is 1.25ns from the last low going data strobe edge to QFC high. And the value of
tQCSW max. is 0.5tcK from the first high going clock edge after the last low going data strobe edge to QFC
high.
6. the value of tQCSWI max. is 1.5tcK from the first high going clock edge after the last low going data strobe
edge to QFC high.
7. A write command can be applied with tRCD satisfied after this command.
Parameter
Symbol
-A2(PC266@CL=2) -B0(PC266@CL=2.5) -A0(PC200@CL=2)
Unit
Note
Min
Max
Min
Max
Min
Max
Exit self refresh to bank active command
tXSA
75
75
80
ns
7
Exit self refresh to read command
tXSR
200
200
200
Cycle
Refresh interval time
64Mb, 128Mb
tREF
15.6
15.6
15.6
us
1
256Mb
7.8
7.8
7.8
us
1
Output DQS valid window
tQH
tHPmin
-0.75ns
-
tHPmin
-0.75ns
-
tHPmin
-1.0ns
-
ns
Clock half period
tHP
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
ns
DQS write postamble time
tWPST
0.25
0.25
0.25
tCK
4
QFC setup to first DQS edge on reads
tQCS
0.9
1.1
0.9
1.1
0.9
1.1
tCK
QFC hold after last DQS edge on reads
tQCH
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write command to QFC delay on write
tQCSW
4.0
4.0
4.0
ns
Write burst end to QFC delay on write
tQCHW
1.25ns
0.5tCK
1.25ns
0.5tCK
1.25ns
0.5tCK
5
Write burst end to QFC delay on write
interrupted by Precharge
tQCHWI
-
1.5tCK
-
1.5tCK
-
1.5tCK
6
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