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參數(shù)資料
| 型號： | KM44V16000C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 16M x 4Bit CMOS Dynamic RAM with Fast Page Mode(16M x 4位CMOS 動態(tài)RAM(帶快速頁模式)) |
| 中文描述： | 16米x 4位與快速頁面模式的CMOS動態(tài)RAM（1,600 × 4位的CMOS動態(tài)隨機存儲器（帶快速頁模式）） |
| 文件頁數(shù)： | 8/20頁 |
| 文件大小： | 344K |
| 代理商： | KM44V16000C |
KM44V16000C,KM44V16100C
CMOS DRAM
NOTES
An initial pause of 200us is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is
achieved.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition times are measured between
V
IH
(min) and V
IL
(max) and are assumed to be 5ns for all inputs.
Measured with a load equivalent to 1 TTL load and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max) can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
≥
t
RCD
(max).
t
OFF
(min)and
t
OEZ
(max) define the time at which the output achieves the open circuit condition and are not referenced V
oh
or V
ol
.
t
WCS
,
t
RWD
,
t
CWD
and
t
AWD
are non restrictive operating parameters. They are included in the data sheet as electric charac-
teristics only. If
t
WCS
≥
t
WCS
(min), the cycles is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If
t
CWD
≥
t
CWD
(min),
t
RWD
≥
t
RWD
(min) and
t
AWD
≥
t
AWD
(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to the CAS falling edge in early write cycles and to the W falling edge in read-modify-write
cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max) can be met.
t
RAD
(max) is specified as a reference point only. If
t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is controlled by
t
AA
.
These specifications are applied in the test mode.
In test mode read cycle, the value of
t
RAC
,
t
AA
,
t
CAC
is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
If
t
RASS
≥
100us, then RAS precharge time must use
t
RPS
instead of
t
RP
.
For RAS-only-Refresh and Burst CAS-before-RAS refresh, 4096 cycles(4K/8K) of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before
and after self refresh in order to meet refresh specification.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
1.
2.
3.
4.
15.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KM48C2000B | 2M x 8Bit CMOS Dynamic RAM with Fast Page Mode |
| KM48C2100B | 2M x 8Bit CMOS Dynamic RAM with Fast Page Mode |
| KM48V2000B | 2M x 8Bit CMOS Dynamic RAM with Fast Page Mode |
| KM48V2100B | 2M x 8Bit CMOS Dynamic RAM with Fast Page Mode |
| KM48C2100C | 2M x 8Bit CMOS Dynamic RAM with Fast Page Mode(2M x 8位CMOS 動態(tài)RAM(帶快速頁模式)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM44V4000AS-6 | 制造商:Samsung Electro-Mechanics 功能描述:Dynamic RAM, Fast Page, 4M x 4, 26 Pin, Plastic, TSOP |
| KM44V4000C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 4Bit CMOS Dynamic RAM with Fast Page Mode |
| KM44V4100AT-7 | 制造商:Samsung Semiconductor 功能描述: |
| KM44V4100C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 4Bit CMOS Dynamic RAM with Fast Page Mode |
| KM470M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:R. F. Molded Chokes |
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