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參數(shù)資料
| 型號(hào)： | KM48C512D |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | High Speed 512K x 8Bit CMOS Dynamic RAM with with Fast Page Mode(高速512K x 8位 CMOS 動(dòng)態(tài)RAM(帶快速頁模式)) |
| 中文描述： | 高速的CMOS為512k × 8位動(dòng)態(tài)隨機(jī)存儲(chǔ)器與快速頁面模式（高速為512k × 8位的CMOS動(dòng)態(tài)隨機(jī)存儲(chǔ)器（帶快速頁模式）） |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 346K |
| 代理商： | KM48C512D |
KM48C512D
CMOS DRAM
High Speed
CAPACITANCE
(T
A
=25
°
C, V
CC
=5V, f=1MHz)
Parameter
Symbol
Min
Max
Units
Input capacitance [A0 ~ A9]
C
IN1
-
5
pF
Input capacitance [RAS, CAS, W, OE]
C
IN2
-
7
pF
Output capacitance [DQ0 - DQ7]
C
DQ
-
7
pF
Test condition : V
CC
=5.0V
±
10%, Vih/Vil=2.8/0.4V, Voh/Vol=2.0/0.8V
Parameter
Symbol
-4
Units
Notes
Min
Max
Random read or write cycle time
t
RC
t
RWC
75
ns
Read-modify-write cycle time
111
ns
Access time from RAS
t
RAC
t
CAC
40
ns
3,4,10
Access time from CAS
12
ns
3,4,5
Access time from column address
t
AA
t
CLZ
20
ns
3,10
CAS to output in Low-Z
0
ns
3
Output buffer turn-off delay
t
OFF
t
T
0
9
ns
6
Transition time (rise and fall)
3
50
ns
2
RAS precharge time
t
RP
t
RAS
25
ns
RAS pulse width
40
10K
ns
RAS hold time
t
RSH
12
ns
CAS hold time
t
CSH
t
CAS
40
ns
CAS pulse width
12
10K
ns
RAS to CAS delay time
t
RCD
t
RAD
18
28
ns
4
RAS to column address delay time
13
20
ns
10
CAS to RAS precharge time
t
CRP
t
ASR
5
ns
Row address set-up time
0
ns
Row address hold time
t
RAH
t
ASC
8
ns
Column address set-up time
0
ns
Column address hold time
t
CAH
t
RAL
10
ns
Column address to RAS lead time
20
ns
Read command set-up time
t
RCS
t
RCH
0
ns
Read command hold time referenced to CAS
0
ns
8
Read command hold time referenced to RAS
t
RRH
t
WCS
0
ns
8
Write command set-up time
0
ns
7
Write command hold time
t
WCH
t
WP
10
ns
Write command pulse width
10
ns
Write command to RAS lead time
t
RWL
t
CWL
12
ns
Write command to CAS lead time
12
ns
AC CHARACTERISTICS
(0
°
C
≤
T
A
≤
60
°
C, See note 1,2)
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