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參數(shù)資料
| 型號(hào)： | KM68S2000 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx8 Bit Low Power and Low Voltage CMOS Static RAM(256K x 8位低功耗和低電壓CMOS 靜態(tài) RAM) |
| 中文描述： | 256Kx8位低功耗和低電壓的CMOS靜態(tài)RAM（256K × 8位低功耗和低電壓的CMOS靜態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 138K |
| 代理商： | KM68S2000 |
CMOS SRAM
Preliminary
KM68S2000 Family
Revision 0.0
September 1997
AC CHARACTERISTICS
(Vcc=2.3~3.3V, Commercial products:T
A
=0 to 70
°
C, Industrial products:T
A
=-40 to85
°
C)
1. The parameter is measured with 30pF test load.
Parameter List
Symbol
Speed Bins
Units
120ns
1)
150ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
120
-
150
-
ns
Address access time
t
AA
-
120
-
150
ns
Chip select to output
t
CO1,
t
CO2
-
120
-
150
ns
Output enable to valid output
t
OE
-
60
-
75
ns
Chip select to low-Z output
t
LZ
20
-
20
-
ns
Output enable to low-Z output
t
OLZ
20
-
20
-
ns
Chip disable to high-Z output
t
HZ
-
35
0
40
ns
Output disable to high-Z output
t
OHZ
-
35
0
40
ns
Output hold from address change
t
OH
15
-
15
-
ns
Write
Write cycle time
t
WC
120
-
150
-
ns
Chip select to end of write
t
CW1,
t
CW2
100
-
120
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
100
-
120
-
ns
Write pulse width
t
WP
80
-
100
-
ns
Write recovery time
t
WR
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
30
0
40
ns
Data to write time overlap
t
DW
50
-
60
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
C
L
1)
1. Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) : C
L
=100pF+1TTL
C
L
=30pF+1TTL
DATA RETENTION CHARACTERISTICS
1. CS
1
≥
Vcc-0.2V, CS
2
≥
Vcc-0.2V(CS
1
Contrlled) or CS
2
≤
0.2V(CS
2
Controlled)
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
1
≥
Vcc-0.2V
1)
2.0
-
3.3
V
Data retention current
I
DR
Vcc=2.0V, CS
1
≥
Vcc-0.2V or CS
2
≤
0.2V
-
-
10
μ
A
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
5
-
-
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| KM68U1000B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128K X 8bit Low Power and Low Voltage CMOS Statinc RAM |
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| KM68U1000BLE/LE-L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128K X 8bit Low Power and Low Voltage CMOS Statinc RAM |
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