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參數(shù)資料
| 型號(hào)： | KM68V1002CI |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128K x 8 Bit High-Speed CMOS Static RAM(3.3V Operating)(128K x 8位高速CMOS 靜態(tài) RAM) |
| 中文描述： | 128K的× 8位高速CMOS靜態(tài)RAM（3.3V的工作）（128K的× 8位高速的CMOS靜態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 131K |
| 代理商： | KM68V1002CI |
KM68V1002C/CL, KM68V1002CI/CLI
CMOS SRAM
PRELIMINARY
Revision 0.0
August 1998
- 6 -
NOTES
(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or
V
OL
levels.
4. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device to
device.
5. Transition is measured
±
200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=V
IL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
cycle.
TIMING WAVEFORM OF WRITE CYCLE(1)
(OE= Clock)
Address
CS
t
WP(2)
t
DW
t
DH
Valid Data
WE
Data in
Data out
t
WC
t
WR(5)
t
AW
t
CW(3)
High-Z(8)
High-Z
OE
t
OHZ(6)
t
AS(4)
Address
CS
t
WP1(2)
t
DW
t
DH
t
OW
t
WHZ(6)
Valid Data
WE
Data in
Data out
t
WC
t
AS(4)
t
WR(5)
t
AW
t
CW(3)
(10)
(9)
High-Z(8)
High-Z
TIMING WAVEFORM OF WRITE CYCLE(2)
(OE=Low Fixed)
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