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參數(shù)資料
| 型號(hào)： | KM736S849 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx36 Synchronous SRAM(256Kx36位同步靜態(tài) RAM) |
| 中文描述： | 256Kx36同步SRAM（256Kx36位同步靜態(tài)內(nèi)存） |
| 文件頁(yè)數(shù)： | 5/17頁(yè) |
| 文件大小： | 279K |
| 代理商： | KM736S849 |
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PRELIMINARY
KM736S849
KM718S949
256Kx36 & 512Kx18 Pipelined N
t
RAM
TM
- 5 -
Rev 0.5
Aug. 1998
FUNCTION DESCRIPTION
The KM736S849 and KM718S949 are N
t
RAM
TM
designed to sustain 100% bus bandwidth by eliminating turnaround cycle when
there is transition from Read to Write, or vice versa.
All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the ADV input. subsequent burst addresses can be internally generated as con-
trolled by the burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new
address for next operation.
Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. All synchronous inputs are ignored
when CKE is high and the internal device registers will hold their previous values.
When CKE is active asserted, ADV is disasserted and all three chip enables(CS
1
, CS
2
, CS
2
) are asserted, N
t
RAM
TM
latches external
address and initiates a cycle.
Output Enable(OE) can be used to disable the output at any given time.
Read operation is initiated when the following conditions are satisfied at the rising edge of clock, CKE is asserted Low, all three chip
enables(CS
1
, CS
2
, CS
2
) are active, the write enable input signals WE is deasserted high, and ADV is asserted Low. The address
presented to the address inputs are latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data a propagate to the input of the output register. At
the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within
provided OE is active Low.
Write operation occurs when WE is sampled Low at the rising edge of clock. BW[d:a] can be used for byte write operation. The Pipe-
lined N
t
RAM
TM
uses a late-late write cycle to utilize 100% of the bandwidth.
At the first rising edge of clock, WE and address are registered, and the data associated with that address is required two cycles
later.
Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst sequence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is Low, linear burst sequence is selected.
And this pin is High, Interleaved burst sequence is selected.
During normal operation, ZZ must be pulled LOW. When ZZ is pulled HIGH, the SRAM will enter a Power Sleep Mode after 2 cycles.
At this time, internal state of the SRAM is preserved. When ZZ returns to LOW, the SRAM normally operates after 2 cycles of wake
up time.
BURST SEQUENCE TABLE
(Interleaved Burst, LBO=High)
Case 1
A
1
A
0
First Address
0
0
1
1
1
LBO PIN
HIGH
Case 2
Case 3
Case 4
A
1
0
0
1
1
A
0
1
0
1
0
A
1
1
1
0
0
A
0
0
1
0
1
A
1
1
1
0
0
A
0
1
0
1
0
Fourth Address
0
1
0
BQ TABLE
(Linear Burst, LBO=Low)
Case 1
A
1
A
0
First Address
0
0
1
1
1
NOTE
: 1. LBO pin must be tied to High or Low, and Floating State must not be allowed
.
LBO PIN
LOW
Case 2
Case 3
Case 4
A
1
0
1
1
0
A
0
1
0
1
0
A
1
1
1
0
0
A
0
0
1
0
1
A
1
1
0
0
1
A
0
1
0
1
0
Fourth Address
0
1
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KM718S949 | 512Kx18 Synchronous SRAM(512Kx18位同步靜態(tài) RAM) |
| KM736V687-10 | x36 Fast Synchronous SRAM |
| KM736V687-8 | x36 Fast Synchronous SRAM |
| KM736V687-9 | x36 Fast Synchronous SRAM |
| KM736V687 | 64Kx36-Bit Synchronous Burst SRAM, 3.3V Power Datasheets for 100TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM736V687 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Kx36-Bit Synchronous Burst SRAM, 3.3V Power Datasheets for 100TQFP |
| KM736V687-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM |
| KM736V687-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM |
| KM736V687-9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM |
| KM736V687A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Kx36 Synchronous SRAM |
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