參數(shù)資料
型號(hào)： KMM5322104CKUG
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 2M x 32 DRAM SIMM using 2Mx8 , 2K Refresh, 5V
中文描述： 200萬(wàn)× 32使用2Mx8 DRAM的上海藥物研究所和2K刷新，5V的
文件頁(yè)數(shù)： 5/15頁(yè)
文件大小： 274K
代理商： KMM5322104CKUG
DRAM MODULE
KMM5322104CKU/CKUG
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
V
IH
(min) and V
IL
(max) are reference levels for measuring
timing of input signals. Transition times are measured
between V
IH
(min) and V
IL
(max) and are assumed to be 5ns
for all inputs.
Measured with a load equivalent to 2 TTL loads and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max)
can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then
access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
≥
t
RCD
(max).
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V
OH
or
V
OL
.
t
WCS
is non-restrictive operating parameter. It is included in
the data sheet as electrical characteristics only. If
t
WCS
≥
t
WCS
(min), the cycle is an early write cycle and the data
out pin will remain high impedance for the duration of the
cycle.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to the CAS leading edge in
early write cycles and to the W leading edge in read-write
cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max)
can be met.
t
RAD
(max) is specified as reference point only. If
t
RAD
is greater than the specified
t
RAD
(max) limit, then
access time is controlled by
t
AA
.
t
CEZ
(max),
t
REZ
(max),
t
WEZ
(max) and
t
OEZ
(max) define the
time at which the output achieves the open circuit condition
and are not referenced to output voltage level.
If RAS goes to high before CAS high going, the open circuit
condtion of the output is achieved by CAS high going. If CAS
goes to high before RAS high going, the open circuit condtion
of the output is achieved by RAS high going.
t
ASC
≥
t
CP min
1.
2.
3.
4.
5.
8.
9.
10.
Test condition : V
ih
/V
il
=2.4/0.8V, V
oh
/V
ol
=2.0/0.8V, output loading CL=100pF
Parameter
Symbol
-5
-6
Unit
Note
Min
Max
30
Min
Max
35
Access time from CAS precharge
Hyper page mode cycle time
CAS precharge time from (Hyper Page Cycle)
RAS pulse width (Hyper Page Cycle)
RAS hold time from CAS precharge
W to RAS precharge time (C-B-R refresh)
W to RAS hold time (C-B-R refresh)
Output data hold time
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
W pulse width (Hyper Page Cycle)
t
CPA
t
HPC
t
CP
t
RASP
t
RHCP
t
WRP
t
WRH
t
DOH
t
REZ
t
WEZ
t
WED
t
WPE
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
13
25
8
50
30
10
10
5
3
3
15
5
30
10
60
35
10
10
5
3
3
15
5
200K
200K
13
13
15
15
6,11,12
6,11
AC CHARACTERISTICS
(0
°
C
≤
T
A
≤
70
°
C, V
CC
=5.0V
±
10%. See notes 1,2.)
11.
12.
13.
6.
7.
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