參數(shù)資料
型號： KMPC8315EVRAGDA
廠商： Freescale Semiconductor
文件頁數(shù)： 67/106頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II 620-PBGA
標準包裝： 2
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 620-BBGA 裸露焊盤
供應商設備封裝： 620-PBGA（29x29）
包裝： 托盤
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
63
PCI Express
Maximum time to
transition to a valid
electrical idle after
sending an electrical idle
ordered set
TTX-IDLE-SET-TO-IDLE After sending an Electrical Idle ordered
set, the Transmitter must meet all
Electrical Idle Specifications within this
time. This is considered a debounce time
for the Transmitter to meet Electrical Idle
after transitioning from L0.
——
20
UI
—
Maximum time to
transition to valid TX
specifications after leaving
an electrical idle condition
TTX-IDLE-TO-DIFF-DATA Maximum time to meet all TX
specifications when transitioning from
Electrical Idle to sending differential data.
This is considered a debounce time for the
TX to meet all TX specifications after
leaving Electrical Idle
——
20
UI
—
Differential return loss
RLTX-DIFF
Measured over 50 MHz to 1.25 GHz.
12
—
dB
4
Common mode return
loss
RLTX-CM
Measured over 50 MHz to 1.25 GHz.
6
—
dB
4
DC differential TX
impedance
ZTX-DIFF-DC
TX DC Differential mode Low Impedance
80
100
120
—
Transmitter DC
impedance
ZTX-DC
Required TX D+ as well as D- DC
Impedance during all states
40
—
—
Lane-to-Lane output skew
LTX-SKEW
Static skew between any two Transmitter
Lanes within a single Link
—
500 + 2
UI
ps
—
AC coupling capacitor
CTX
All Transmitters shall be AC coupled. The
AC coupling is required either within the
media or within the transmitting
component itself.
75
—
200
nF
8
Crosslink random timeout
Tcrosslink
This random timeout helps resolve
conflicts in crosslink configuration by
eventually resulting in only one
Downstream and one Upstream Port.
0—
1
ms
7
Note:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 52 and measured over any 250
consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 50.)
3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the transmitter
collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total TX jitter budget
collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes
the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value.
4. The transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode return loss
greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid
input levels. The reference impedance for return loss measurements is 50
to ground for both the D+ and D– line (that is, as measured
by a vector network analyzer with 50-
probes, see Figure 52). Note that the series capacitors, C
TX, is optional for the return loss
measurement.
5. Measured between 20%–80% at transmitter package pins into a test load as shown in Figure 52 for both VTX-D+ and VTX-D-.
6. See Section 4.3.1.8 of the PCI Express Base Specifications, Rev 1.0a.
7. See Section 4.2.6.3 of the PCI Express Base Specifications, Rev 1.0a.
8. MPC8315E SerDes transmitter does not have CTX built-in. An external AC Coupling capacitor is required
Table 54. Differential Transmitter (TX) Output Specifications (continued)
Parameter
Symbol
Comments
Min
Typical
Max
Unit
Note
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