參數(shù)資料
型號： KMPC8315EVRAGDA
廠商： Freescale Semiconductor
文件頁數(shù)： 96/106頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II 620-PBGA
標(biāo)準(zhǔn)包裝： 2
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 620-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 620-PBGA（29x29）
包裝： 托盤
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
9
Electrical Characteristics
3.1.2
Power Supply Voltage Specification
This table provides the recommended operating conditions for theMPC8315E. Note that the values in this
table are the recommended and tested operating conditions. Proper device operation outside of these
conditions is not guaranteed.
Input voltage
DDR DRAM signals
MVIN
–0.3 to (GVDD + 0.3)
V
2, 4
DDR DRAM reference
MVREF
–0.3 to (GVDD + 0.3)
V
2, 4
eTSEC signals
LVIN
–0.3 to (LVDD + 0.3)
V
3, 4
Local bus, DUART, SYS_CLK_IN, system
control and power management, I2C, and
JTAG signals
NVIN
–0.3 to (NVDD + 0.3)
V
3, 4
PCI
NVIN
–0.3 to (NVDD + 0.3)
V
5
SATA_CLKIN
NVIN
–0.3 to (NVDD + 0.3)
V
3, 4
Storage temperature range
TSTG
–55 to150
C—
Note:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3. Caution: (N,L)VIN must not exceed (N,L)VDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms
during power-on reset and power-down sequences.
4. (M,N,L)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
5. NVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as
shown in Figure 2.
6. The max value of supply voltage should be selected based on the RGMII mode.
7. NVDD means NVDD1_OFF, NVDD1_ON, NVDD2_OFF, NVDD2_ON, NVDD3_OFF, NVDD4_OFF
8. LVDD means LVDD1_OFF and LVDD2_ON
Table 2. Recommended Operating Conditions
Characteristic
Symbol
Recommended
Value1
Unit
Status in D3
Warm mode
Note
SerDes internal digital power
XCOREVDD
1.0 ± 50 mv
V
Switched Off
—
SerDes internal digital power
XCOREVSS
0.0
V
—
SerDes I/O digital power
XPADVDD
1.0 ± 50 mv
V
Switched Off
—
SerDes I/O digital power
XPADVSS
0.0
V
—
SerDes analog power for PLL
SDAVDD
1.0 ± 50 mv
V
Switched Off
—
SerDes analog power for PLL
SDAVSS
0.0
V
—
Dedicated 3.3 V analog power for USB PLL
USB_PLL_PWR3
3.3 ± 165mv
V
Switched Off
—
Dedicated 1.0 Vanalog power for USB PLL
USB_PLL_PWR1
1.0 ± 50 mv
V
Switched Off
—
Dedicated analog ground for USB PLL
USB_PLL_GND
0.0
V
—
Dedicated USB power for USB bias circuit
USB_VDDA_BIAS
3.3 ± 300 mv
V
Switched Off
—
Table 1. Absolute Maximum Ratings 1 (continued)
Characteristic
Symbol
Max Value
Unit
Note
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