參數(shù)資料
型號(hào): KMPC8358EZQAGDGA
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 57/95頁(yè)
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II 668-PBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 668-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 668-PBGA-PGE(29x29)
包裝: 托盤
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
60
Freescale Semiconductor
UTOPIA/POS
Figure 45 provides the AC test load for the UTOPIA.
Figure 45. UTOPIA AC Test Load
Figure 46 and Figure 47 represent the AC timing from Table 55. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Figure 46 shows the UTOPIA timing with external clock.
Figure 46. UTOPIA AC Timing (External Clock) Diagram
UTOPIA inputs—External clock input setup time
tUEIVKH
4.2
ns
UTOPIA inputs—Internal clock input hold time
tUIIXKH
2.4
ns
UTOPIA inputs—External clock input hold time
tUEIXKH
1—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUIKHOX symbolizes the UTOPIA
outputs internal timing (UI) for the time tUTOPIA memory clock reference (K) goes from the high state (H) until outputs (O) are
invalid (X).
Table 59. UTOPIA AC Timing Specifications1 (continued)
Characteristic
Symbol2
Min
Max
Unit
Notes
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
UtopiaCLK (Input)
tUEIXKH
tUEIVKH
tUEKHOV
Input Signals:
UTOPIA
Output Signals:
UTOPIA
tUEKHOX
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