參數(shù)資料
型號(hào): KMPC8358EZQAGDGA
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 88/95頁(yè)
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II 668-PBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 668-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 668-PBGA-PGE(29x29)
包裝: 托盤
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
Freescale Semiconductor
89
System Design Information
23.3.1
Experimental Determination of the Junction Temperature with a
Heat Sink
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
TJ = TC + (RθJC × PD)
where:
TJ = junction temperature (°C)
TC = case temperature of the package (°C)
RθJC = junction to case thermal resistance (°C/W)
PD = power dissipation (W)
24 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8358E. Additional information can be found in MPC8360E/MPC8358E PowerQUICC Design
Checklist (AN3097).
24.1
System Clocking
The device includes two PLLs, as follows.
The platform PLL (AVDD1) generates the platform clock from the externally supplied CLKIN
input. The frequency ratio between the platform and CLKIN is selected using the platform PLL
ratio configuration bits as described in Section 22.1, “System PLL Configuration.
The e300 core PLL (AVDD2) generates the core clock as a slave to the platform clock. The
frequency ratio between the e300 core clock and the platform clock is selected using the e300 PLL
ratio configuration bits as described in Section 22.2, “Core PLL Configuration.
24.2
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1,
AVDD2, respectively). The AVDD level should always be equivalent to VDD, and preferably these voltages
will be derived directly from VDD through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in Figure 54, one to each of the five AVDD pins. By
providing independent filters to each PLL, the opportunity to cause noise injection from one PLL to the
other is reduced.
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