參數(shù)資料
型號(hào): KMPC8544EVTAQG
廠商: Freescale Semiconductor
文件頁數(shù): 26/117頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC III 783-PBGA
標(biāo)準(zhǔn)包裝: 5
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
16
Freescale Semiconductor
RESET Initialization
4.5
Other Input Clocks
For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC,
see the specific section of this document.
5
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8544E. Table 8 provides the RESET initialization AC timing specifications for the DDR SDRAM
component(s).
Table 9 provides the PLL lock times.
6
DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8544E. Note that DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.
Table 8. RESET Initialization Timing Specifications1
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HREST
100
μs—
Minimum assertion time for SRESET
3
SYSCLKs
1
PLL input setup time with stable SYSCLK before HRESET
negation
100
μs—
Input setup time for POR configs (other than PLL config) with
respect to negation of HRESET
4
SYSCLKs
1
Input hold time for all POR configs (including PLL config) with
respect to negation of HRESET
2
SYSCLKs
1
Maximum valid-to-high impedance time for actively driven POR
configs with respect to negation of HRESET
5
SYSCLKs
1
Note:
1. SYSCLK is the primary clock input for the MPC8544E.
Table 9. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
Core and platform PLL lock times
100
μs—
Local bus PLL
50
μs—
PCI bus lock time
50
μs—
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