參數(shù)資料
型號: KMPC8544EVTAQG
廠商: Freescale Semiconductor
文件頁數(shù): 84/117頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC III 783-PBGA
標準包裝: 5
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應商設備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
69
High-Speed Serial Interfaces (HSSI)
Figure 49 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It
assumes that the DC levels of the clock driver chip is compatible with MPC8544E SerDes reference clock
input’s DC requirement.
Figure 49. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
Figure 50 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.
Since LVDS clock driver’s common mode voltage is higher than the MPC8544E SerDes reference clock
input’s allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the
LVDS output driver features 50-
Ω termination resistor. It also assumes that the LVDS transmitter
establishes its own common mode level without relying on the receiver or other external component.
Figure 50. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)
Figure 51 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.
Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with
MPC8544E SerDes reference clock input’s DC requirement, AC-coupling has to be used. Figure 51
50
Ω
50
Ω
SDn_REF_CLK
Clock Driver
100
Ω differential PWB trace
Clock driver vendor dependent
source termination resistor
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
HCSL CLK Driver Chip
33
Ω
33
Ω
Total 50
Ω. Assume clock driver’s
output impedance is about 16
Ω.
CLK_Out
MPC8544E
50
Ω
50
Ω
SDn_REF_CLK
Clock Driver
100
Ω differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
LVDS CLK Driver Chip
10 nF
MPC8544E
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