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參數(shù)資料
| 型號： | KMPC8555EVTALF |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 81/88頁 |
| 文件大小： | 0K |
| 描述： | IC MPU POWERQUICC III 783-FCPBGA |
| 標準包裝： | 1 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 667MHz |
| 電壓： | 1.2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
82
Freescale Semiconductor
System Design Information
The COP function of these processors allow a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order
to fully control the processor. If the target system has independent reset sources, such as voltage monitors,
watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be
merged into these signals with logic.
The arrangement shown in Figure 52 allows the COP port to independently assert HRESET or TRST,
while ensuring that the target can drive HRESET as well.
The COP interface has a standard header, shown in Figure 52, for connection to the target system, and is
based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The
connector typically has pin 14 removed as a connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features. An inexpensive option can be to leave
the COP header unpopulated until needed.
There is no standardized way to number the COP header; consequently, many different pin numbers have
been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others
use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as
with an IC). Regardless of the numbering, the signal placement recommended in Figure 52 is common to
all known emulators.
Figure 52. COP Connector Physical Pinout
3
13
9
5
1
6
10
15
11
7
16
12
8
4
KEY
No pin
1
2
COP_TDO
COP_TDI
NC
COP_TRST
COP_VDD_SENSE
COP_CHKSTP_IN
NC
GND
COP_TCK
COP_TMS
COP_SRESET
COP_HRESET
COP_CHKSTP_OUT
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參數(shù)描述 |
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| KMPC8555EVTAPF | 功能描述:微處理器 - MPU PQ 37 LITE 8555E RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| KMPC8555EVTAQF | 功能描述:微處理器 - MPU PQ 37 LITE 8555E RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| KMPC8555PXALF | 功能描述:微處理器 - MPU PQ 37 LITE 8555 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| KMPC8555PXAPF | 功能描述:微處理器 - MPU PQ 37 LITE 8555 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| KMPC8555PXAQF | 功能描述:微處理器 - MPU PQ 37 LITE 8555 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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