參數(shù)資料
型號: KMPC8555VTAQF
廠商: Freescale Semiconductor
文件頁數(shù): 26/88頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC III 783-FCPBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1.3V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
32
Freescale Semiconductor
Ethernet: Three-Speed, MII Management
8.3.2
MII Management AC Electrical Specifications
Table 28 provides the MII management AC timing specifications.
Input high current
IIH
LVDD = Max
VIN
1 = 2.1 V
40
μA
Input low current
IIL
LVDD = Max
VIN = 0.5 V
–600
μA
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
Table 28. MII Management AC Timing Specifications
At recommended operating conditions with LVDD is 3.3 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Notes
MDC frequency
fMDC
0.893
10.4
MHz
2
MDC period
tMDC
96
1120
ns
MDC clock pulse width high
tMDCH
32
ns
MDC to MDIO valid
tMDKHDV
2*[1/(fccb_clk/8)]
ns
3
MDC to MDIO delay
tMDKHDX
10
2*[1/(fccb_clk/8)]
ns
3
MDIO to MDC setup time
tMDDVKH
5—
ns
MDIO to MDC hold time
tMDDXKH
0—
ns
MDC rise time
tMDCR
10
ns
MDC fall time
tMDHF
10
ns
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX
symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are
invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input
signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For
rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the system clock speed (that is, for a system clock of 267 MHz, the delay is 70 ns and for
a system clock of 333 MHz, the delay is 58 ns).
3. This parameter is dependent on the CCB clock speed (that is, for a CCB clock of 267 MHz, the delay is 60 ns and for a
CCB clock of 333 MHz, the delay is 48 ns).
4. Guaranteed by design.
Table 27. MII Management DC Electrical Characteristics (continued)
Parameter
Symbol
Conditions
Min
Max
Unit
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