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參數資料
| 型號： | KMPC8555VTAQF |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 76/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU POWERQUICC III 783-FCPBGA |
| 標準包裝： | 2 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 1.0GHz |
| 電壓： | 1.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，FCBGA |
| 供應商設備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
78
Freescale Semiconductor
System Design Information
17 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8555E.
17.1
System Clocking
The MPC8555E includes five PLLs.
1. The platform PLL (AVDD1) generates the platform clock from the externally supplied SYSCLK
input. The frequency ratio between the platform and SYSCLK is selected using the platform PLL
ratio configuration bits as described in Section 15.2, “Platform/System PLL Ratio.”
2. The e500 Core PLL (AVDD2) generates the core clock as a slave to the platform clock. The
frequency ratio between the e500 core clock and the platform clock is selected using the e500
PLL ratio configuration bits as described in Section 15.3, “e500 Core PLL Ratio.”
3. The CPM PLL (AVDD3) is slaved to the platform clock and is used to generate clocks used
internally by the CPM block. The ratio between the CPM PLL and the platform clock is fixed and
not under user control.
4. The PCI1 PLL (AVDD4) generates the clocking for the first PCI bus.
5. The PCI2 PLL (AVDD5) generates the clock for the second PCI bus.
17.2
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1,
AVDD2, AVDD3, AVDD4, and AVDD5 respectively). The AVDD level should always be equivalent to VDD,
and preferably these voltages are derived directly from VDD through a low frequency filter scheme such
as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in Figure 50, one to each of the five AVDD pins. By
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of the 783 FC-PBGA footprint, without the inductance of vias.
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