參數(shù)資料
型號(hào)： KMPC8560VT833LB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 5/36頁(yè)
文件大?。?/td> 0K
描述： IC MPU POWERQUICC III 783-FCPBGA
標(biāo)準(zhǔn)包裝： 2
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 833MHz
電壓： 1.2V
安裝類型： 表面貼裝
封裝/外殼： 784-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
MOTOROLA
MPC8560 PowerQUICC III
13
Integrated Communications Processor Product Brief
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
On-Chip Memory Unit
activities. The CP has an instruction set optimized for communications but that can also be used for
general-purpose applications, relieving the system core of small, often repeated tasks.
Two serial DMAs (SDMAs), one associated with the local bus and one associated with the e500
coherency module (ECM), handling transfers simultaneously
Three full-duplex, serial FCCs supporting ATM (155 Mbps) protocol through two UTOPIA L2
interfaces, IEEE 802.3 and fast Ethernet protocols, HDLC up to E3 rates (45 Mbps) and totally
transparent operation. Each FCC can be configured to transmit fully-transparent data and receive
HDLC data, or vice-versa.
Two MCCs capable of handling an aggregate of 256 64-Kbps HDLC or transparent channels,
multiplexed on up to 8 TDM interfaces. The MCC also supports super-channels of rates higher than
64 Kbps and subchanneling of the 64-Kbps channels.
Four full-duplex SCCs supporting high-level synchronous data link control, HDLC, local talk,
UART, synchronous UART, BISYNC, and transparent
SPI and I2C bus controllers
TSA that supports multiplexing of data from any of the four SCCs and three FCCs
ATM TC-layer functionality is implemented internally to support applications that receive ATM
traffic over standard serial protocols (T1, E1, xDSL) through their serial interface ports
3.3
On-Chip Memory Unit
The MPC8560 contains an internal 256-Kbyte memory array that can be configured as memory-mapped
SRAM or as a look-aside L2 cache. The array can also be divided into two 128-Kbyte arrays, one of which
may be used as cache and the other as SRAM.
The memory controller for this array connects to the core complex bus (CCB) and communicates through
128-bit read and write buses to the e500 core and the MPC8560 system logic.
The on-chip memory unit contains:
256 Kbytes of on-chip memory
— L2 cache partitioning is configurable
— Can act as a 256-Kbyte L2 cache
— 256-Kbyte array organized as 1024 eight-way sets of 32-byte cache lines
— Array can be partitioned into 128-Kbyte L2 cache and 128-Kbyte memory mapped SRAM
— Can act as two 128-Kbyte memory-mapped SRAM arrays or a 256-Kbyte SRAM region
— SRAM operation is byte-accessible
— Data ECC on 64-bit boundaries (single-error correction, double-error detection)
— Tag parity (1 bit covering all tag bits)
— Cache mode supports instruction caching, data caching, or both
— External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types
— Separate locking for instructions and data so that locks can be set and cleared separately
— Supports locking the entire cache or selected lines
— Individual line locks are set and cleared through core-initiated instructions, by external reads or
writes, or by accesses to programmed memory ranges
— Flash clearing done through writes to L2 configuration registers
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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