參數(shù)資料
型號(hào)： KMPC8560VT833LB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 9/36頁(yè)
文件大?。?/td> 0K
描述： IC MPU POWERQUICC III 783-FCPBGA
標(biāo)準(zhǔn)包裝： 2
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 833MHz
電壓： 1.2V
安裝類型： 表面貼裝
封裝/外殼： 784-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
MOTOROLA
MPC8560 PowerQUICC III
17
Integrated Communications Processor Product Brief
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Integrated DMA
The MPC8560 TSECs support programmable CRC generation and checking, RMON statistics, and jumbo
frames of up to 9.6 Kbytes. Frame headers and buffer descriptors can be forced into the L2 cache to speed
classification or other frame processing.
3.11 Integrated DMA
The MPC8560 DMA engine is capable of transferring blocks of data from any legal address range to any
other legal address range. Therefore, it can perform a DMA transfer between any of its I/O or memory ports
or even between two devices or locations on the same port.
The four-channel DMA controller allows chaining (both extended and direct) through local
memory-mapped chain descriptors. Scattering, gathering, and misaligned transfers are supported. In
addition, advanced capabilities such as stride transfers and complex transaction chaining are supported.
DMA transfers can be initiated by a single write to a configuration register. There is also support for external
control of transfers using DMA_DREQ, DMA_DACK, and DMA_DDONE handshake signals.
DMA descriptors encompass a rich set of attributes that allow DMA transfers to bypass outbound address
translation and supply external addresses and attributes directly to the RapidIO port. Local attributes such
as snoop and L2-write stashing can be specified by descriptors.
Interrupts are provided on a completed segment, link, list, chain, or on an error condition. Coherency is
selectable and hardware enforced (snoop/no snoop).
3.12 PCI Controller
The MPC8560 64-bit PCI controller is compatible with the PCI Local Bus Specification, Revision 2.2 and
the PCI-X Addendum, Revision 1.0. The interface can function as a host or agent bridge interface in either
PCI or PCI-X mode. Both PCI and PCI-X modes support 64-bit addressing and 32-bit or 64-bit data buses.
As a master, the MPC8560 supports read and write operations to the PCI memory space, the PCI I/O space,
and the PCI configuration space. Also, the MPC8560 can generate PCI special-cycle and
interrupt-acknowledge commands. As a target, the MPC8560 supports read and write operations to system
memory as well as configuration accesses.
PCI-X functionality includes split transaction support for four outstanding split transactions. Split response
data is returned in order without interleaving. As a target, the MPC8560 supports all PCI-X sizes. As a
master it internally combines transactions up to 256 bytes.
An internal arbiter can be used to support up to five external masters. A round robin arbitration algorithm
with two priority levels is used.
3.13 RapidIO Controller
The RapidIO interconnect unit on the MPC8560 is based on the RapidIO Interconnect Specification,
Revision 1.1. RapidIO is a high-performance, point-to-point, low-pin-count, packet-switched system-level
interconnect that can be used in a variety of applications as an open standard. The RapidIO architecture
provides a rich variety of features including high data bandwidth, low-latency capability, and support for
high-performance I/O devices, as well as providing message-passing and software-managed programming
models.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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