參數(shù)資料
型號(hào): KMPC8560VTAQFB
廠商: Freescale Semiconductor
文件頁數(shù): 12/36頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC III 783-FCPBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1.3V
安裝類型: 表面貼裝
封裝/外殼: 784-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
2
MPC8560 PowerQUICC III
MOTOROLA
Integrated Communications Processor Product Brief
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Key Features
Part II MPC8560 Overview
The following section provides a high-level overview of the features of the MPC8560.
Figure 1 shows the major functional units in the MPC8560.
Figure 1. MPC8560 Block Diagram
2.1
Key Features
The following is an overview of the MPC8560 feature set.
High-performance, 32-bit Book E–enhanced core that implements the PowerPC architecture
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can
be locked entirely or on a per-line basis, with separate locking for instructions and data.
— Signal-processing engine (SPE) auxiliary processing unit (APU) provides an extensive
instruction set for vector (64-bit) integer, single-precision floating-point, and fractional
operations. These instructions use both the upper and lower words of the 64-bit GPRs as they
are defined by the SPE APU.
MII, GMII, TBI,
RTBI, RGMIIs
ROM
I-Memory
DPRAM
RISC
Engine
T
C
-Layer
MPHY
MIIs/RMIIs
TDMs
I/Os
Core Complex
16 Gb/s
RapidIO-8
133 MHz
PCI-X 64b
IRQs
SDRAM
DDR
GPIO
32b
UTOPIAs
Bus
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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