參數(shù)資料
型號(hào)： KS8721BLI TR
廠商： Micrel Inc
文件頁(yè)數(shù)： 6/35頁(yè)
文件大小： 0K
描述： TXRX 10/100 3.3V 48-LQFP
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： MII，RMII
電源電壓： 2.375 V ~ 2.625 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
配用： 576-1007-ND - BOARD EVAL EXPERIMENT KS8721BL
其它名稱(chēng)： KS8721BLITR
KS8721BLITR-ND
Micrel, Inc.
KS8721BL/SL
June 2009
14
M9999-062509-1.3
Reference Clock (REF_CLK)
REF_CLK is a continuous 50MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN, TXD[1:0],
and RX_E. REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide
REF_CLK as an input or an output depending on whether they provide a REF_CLK output or rely on an external clock
distribution device. Each PHY device must have an input corresponding to this clock but may use a single clock input
for multiple PHYs implemented on a single IC.
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is,
in 10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 noncontiguous zeroes in 10 bits are
detected, the carrier is detected.
Loss-of-carrier results in the de-assertion of CRS_DV synchronous to REF_CLK. As carrier criteria are met, CRS_DV
remains continuously asserted from the rst recovered di-bit of the frame through the nal recovered di-bit and is
negated prior to the rst REF_CLK that follows the nal di-bit.
The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is
asynchronous relative to REF_CLK, the data on RXD[1:0] remains as “00” until proper receive signal decoding takes
place (see “Denition of RXD[1:0] Behavior”).
Receive Data [1:0] (RXD[1:0])
RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0]
transfers two bits of recovered data from the PHY. In some cases (e.g., before data recovery or during error conditions),
a predetermined value for RXD[1:0] is transferred instead of recovered data. RXD[1:0] remains as “00” to indicate idle
when CRS_DV is de-asserted. Values of RXD[1:0] other than “00” when CRS_DV is de-asserted are reserved for out-
of-band signaling (to be dened). Values other than “00” on RXD[1:0] while CRS_DV is de-asserted are ignored by the
MAC/repeater. Upon assertion of CRS_DV, the PHY ensures that RXD[1:0]=00 until proper receive decoding takes
place.
Transmit Enable (TX_EN)
Transmit Enable TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] on the RMII for transmission. TX_EN
is asserted synchronously with the rst nibble of the preamble and remains asserted while all transmitted di-bits are
presented to the RMII. TX_EN is negated prior to the rst REF_CLK following the nal di-bit of a frame. TX_EN
transitions synchronously with respect to REF_CLK.
Transmit Data [1:0] (TXD[1:0])
Transmit Data TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are
accepted for transmission by the PHY. TXD[1:0] remains as “00” to indicate idle when TX_EN is de-asserted. Values of
TXD[1:0] other than “00” when TX_EN is de-asserted are reserved for out-of-band signaling (to be dened). Values
other than “00” on TXD[1:0] while TX_EN is de-asserted are ignored by the PHY.
Collision Detection
Since the denition of CRS_DV and TX_EN both contain an accurate indication of the start of frame, the MAC reliably
re-generates the COL signal of the MII by ANDing TX_EN and CRS_DV.
During the IPG time following the successful transmission of a frame, the COL signal is asserted by some transceivers
as a self-test. The Signal Quality Error (SQE) function is not supported by the reduced MII due to the lack of the COL
signal. Historically, SQE was present to indicate that a transceiver located physically remote from the MAC was
functioning. Since the reduced MII only supports chip-to-chip connections on a PCB, SQE functionality is not required.
RX_ER
The PHY provides RX_ER as an output according to the rules specied in IEEE 802.3u [2] (see Clause 24, Figure 24-
11– Receive State Diagram). RX_ER is asserted for one or more REF_CLK periods to indicate that an error (e.g., a
coding error or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sub-
layer) is detected somewhere in the frame presently being transferred from the PHY. RX_ER transitions synchronously
with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER has no effect on the MAC.
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