Type(1) Port Pin Function 97 LED3-1 Ipu" />
參數(shù)資料
型號： KS8995MI
廠商： Micrel Inc
文件頁數(shù)： 8/73頁
文件大?。?/td> 0K
描述： IC SWITCH 10/100 5PORT 128PQFP
標(biāo)準(zhǔn)包裝： 66
系列： *
類型： *
應(yīng)用： *
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 散裝
其它名稱： 576-1020
KS8995M
Micrel
M9999-120403
16
December 2003
Pin Number
Pin Name
Type(1)
Port
Pin Function
97
LED3-1
Ipu/O
3
LED indicator 1
96
LED3-2
Ipu/O
3
LED indicator 2
95
LED4-0
Ipu/O
4
LED indicator 0
94
LED4-1
Ipu/O
4
LED indicator 1
93
LED4-2
Ipu/O
4
LED indicator 2
92
LED5-0
Ipu/O
5
LED indicator 0
91
LED5-1
Ipu/O
5
LED indicator 1. Strap option: PU (default): enable PHY MII I/F.
PD: tristate all PHY MII output. See
“pin# 86 SCONF1.”
90
LED5-2
Ipu/O
5
LED indicator 2. Strap option: Aging setup. See
“Aging” section.
(default) = Aging Enable; PD = Aging disable
107
MDC
Ipu
All
Switch or PHY[5] MII management data clock.
108
MDIO
I/O
All
Switch or PHY[5] MII management data I/O.
1
TEST1
NC
NC for normal operation. Factory test pin.
45
MUX1
NC
MUX1 and MUX2 should be left unconnected for normal operation.
46
MUX2
NC
They are factory test pins.
Mode
Mux1
Mux2
Normal Operation
NC
Remote Analog Loopback Mode for Testing only
0
1
Reserved
1
0
Power Save Mode for Testing only
1
68
PCOL
Ipd/O
5
PHY[5] MII collision detect/Force flow control. See
“Register 18.”
For port 4 only. PD (default) = No force flow control. PU = Force flow
control.
67
PCRS
Ipd/O
5
PHY[5] MII carrier sense/Force duplex mode See
“Register 28.”
For port 4 only. PD (default) = Force half-duplex if auto-negotiation is
disabled or fails. PU = Force full-duplex if auto-negotiation is disabled
or fails.
60
PMRXC
O
5
PHY[5] MII receive clock. PHY mode MII.
65
PMRXD0
Ipd/O
5
PHY[5] MII receive bit 0. Strap option: PD (default) = disable
aggressive back-off algorithm in half-duplex mode; PU = enable for
performance enhancement.
64
PMRXD1
Ipd/O
5
PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive
collision packets; PU = does not drop excessive collision packets.
63
PMRXD2
Ipd/O
5
PHY[5] MII receive bit 2. Strap option: PD (default) = disable back
pressure; PU = enable back pressure.
62
PMRXD3
Ipd/O
5
PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow
control; PU = disable flow control.
Note:
1. P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/ internal pull-up
Ipd = Input w/ internal pull-down
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pin pull-down
Otri = Output tristated
NC = No Connect
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KS8995X 功能描述:IC SWITCH 10/100 5PORT 128PQFP RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
KS8995X_04 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Integrated 5-Port 10/100 QoS Switch
KS8995XA 功能描述:IC SWITCH 10/100 5PORT 128PQFP RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
KS8995XA_11 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Integrated 5-Port 10/100 QoS Switch
KS8995XA4 功能描述:IC SWITCH 5-PORT 10/100 128-PQFP RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
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