參數(shù)資料
型號： KSZ8001LI TR
廠商： Micrel Inc
文件頁數(shù)： 10/46頁
文件大小： 0K
描述： IC TXRX PHY 10/100 3.3V 48LQFP
標準包裝： 1,000
類型： 收發(fā)器
規(guī)程： MII，RMII，SMII
電源電壓： 1.8V, 3.3V
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應商設備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
Micrel
KSZ8001
June 2009
Revision 1.04
18
CRS
RX_DV
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
X
0
RX_ER
from
previous
frame
Speed
0=10Mbit
1=100Mbit
Duplex
0=Half
1=Full
Link
0=Down
1=Up
Jabber
0=OK
1=Error
Upper
Nibble
0=invalid
1=valid
False
Carrier
Detected
1
X
1
One Data Byte (Two MII Data Nibble)
TXD7 – 0 Encoding
Inter-frame status bit RXD5 conveys the validity of the upper nibble of the byte of the previous frame. Inter-frame status bit RXD0
indicates whether or not the PHY detected an error somewhere on the previous frame. Both of these bits should be valid in the
segment immediately following a frame, and should stay valid until the first data segment of the next frame begins.
When asserted, inter-frame status bit RXD6 indicates that the PHY has detected a false carrier event.
In order to send receive data to the MAC synchronous to the reference clock, the PHY must pass the data through an elasticity FIFO
to handle any difference between the reference clock rate and the clock at the packet source. The Ethernet specification calls for
packet data to be referenced to a clock with a frequency tolerance of 100ppm (0.01%); however, it is not uncommon to encounter
Ethernet stations with clocks that have frequency errors up to 0.1%. Therefore, the elasticity FIFO should be at least 27 bits * long,
filling to the halfway point before beginning valid data transfer via RX. RX_ER should be asserted if, during the reception of a frame,
this FIFO overflows or underflows.
Only RXD and RX_DV should be passed through the elasticity FIFO. CRS should not be passed through the elasticity FIFO. Instead,
CRS should be asserted for the time the ‘wire’ is busy receiving a frame.
Transmit Path
Transmit data and control information are signaled in ten bit segments, just like the receive path. In 100Mbit mode, each segment
represents anew byte of data. In 10Mbit mode each segment is repeated ten times; therefore, every ten segments represents a new
byte of data. The PHY can sample any one of every 10 segments in 10Mbit mode.
Segment boundaries are delimited by SYNC. The MAC continuously generates a pulse on SYNC every 10 clocks.
Transmit Sequence Diagram
T X _E R
T X _E N
TX D 0
TX D 1
TX D 2
TX D 3
TX D 4
T X D 5
TX D 6
T X D 7
TX _C LK
TX _S Y N C
TX
Bits
Purpose
TX_EN
Transmit Enable – identical to MII
TX_ER
Transmit Error – identical to MII
TXD7-0
Encoded Data – see TXD7-0 Encoding Table
TX- Bit Description
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