參數(shù)資料
型號： KSZ8001LI TR
廠商： Micrel Inc
文件頁數(shù)： 9/46頁
文件大?。?/td> 0K
描述： IC TXRX PHY 10/100 3.3V 48LQFP
標準包裝： 1,000
類型： 收發(fā)器
規(guī)程： MII，RMII，SMII
電源電壓： 1.8V, 3.3V
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應商設備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
Micrel
KSZ8001
June 2009
Revision 1.04
17
SMII Signal Definition
SMII is composed of two signals per port, a global synchronization signal, and a global 125MHz reference clock. All signals are
synchronous to the clock. All SMII I/F uses a common 125MHz reference clock and SYNC signals that are synchronous to the
reference clock. There are two signals in SMII from MAC-to-PHY for each port (TXD and TxSYNC), and one signal per port from
PHY-to-MAC (RXD).
The Serial Media Independent Interface (SMII) is designed to satisfy the following requirements:
Convey complete MII information between a 10/100 PHY and MAC with two pins per port.
Allow a multi-port MAC/PHY communication with one system clock.
Operate in both half and full duplex.
Per packet switching between 10Mbit and 100Mbit data rates.
Allow direct MAC-to-MAC communication.
SMII Signals
Signal Name
From
To
Use
RX
PHY
MAC
Receive Data and Control
TX
MAC
PHY
Transmit Data and Control
SYNC
MAC
PHY
Synchronization
Clock
System
MAC&PHY
Synchronization
Receive Path
Receive data and control information are signaled in ten bit segments. In 100Mbit mode, each segment represents a new byte of
data. In 10Mbit mode, each segment is repeated ten times; therefore, every ten segments represent a new byte of data. The MAC
can simply any one of every 10 segment ion 10Mbit mode.
Segment boundaries are delimited by SYNC. The MAC continuously generates a pulse on SYNC every 10 clocks.
Receive Sequence Diagram
C R S
R X _ D V
R XD 0
R XD 1
R XD 2
R XD 3
R XD 4
R XD 5
R XD 6
R X D 7
R X _C LK
RX _ S Y N C
RX
RX contains all of the information found on the receive path of the standard MII.
Bits
Purpose
CRS
Carrier Sense – identical to MII, except that it is not an asynchronous signal
RX_DV
Receive Data Valid – identical to MII
RXD7-0
Encoded Data, see the RXD0-7 Encoding table
RX – Bit Description
RXD7-0 are used to convey packet data, RX_ER, and PHY status. The MAC can infer the meaning of RXD on a segment-by-basis
by encoding the two control bits.
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