Cable Diagnostics The Link" />
參數(shù)資料
型號： KSZ8031RNLI
廠商： Micrel Inc
文件頁數(shù)： 14/43頁
文件大?。?/td> 0K
描述： TXRX PHY 10/100 3.3V 24-QFN
標(biāo)準(zhǔn)包裝： 75
類型： PHY 收發(fā)器
驅(qū)動器/接收器數(shù)： 1/1
規(guī)程： RMII
電源電壓： 1.8V，2.5V，3.3V
安裝類型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 24-QFN（4x4）
包裝： 管件
配用： 576-3862-ND - BOARD EVALUATION FOR KSZ8031RNL
其它名稱： 576-3788
Micrel, Inc.
KSZ8021RNL / KSZ8031RNL
August 2010
21
M9999-082710-1.0
LinkMD
Cable Diagnostics
The LinkMD
function utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems,
such as open circuits, short circuits and impedance mismatches.
LinkMD
works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, and then analyzing the
shape of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides the
approximate distance to the cabling fault. The LinkMD
function processes this TDR information and presents it as a
numerical value that can be translated to a cable distance.
LinkMD
is initiated by accessing register 1Dh, the LinkMD Control/Status Register, in conjunction with register 1Fh, the
PHY Control 2 Register. The latter register is used to disable auto MDI/MDI-X and to select either MDI or MDI-X as the
cable differential pair for testing.
NAND Tree Support
The KSZ8021/31RNL provides parametric NAND tree support for fault detection between chip I/Os and board. The NAND
tree is a chain of nested NAND gates in which each KSZ8021/31RNL digital I/O (NAND tree input) pin is an input to one
NAND gate along the chain. At the end of the chain, the TXD1 pin provides the output for the nested NAND gates.
The NAND tree test process includes:
Enabling NAND tree mode
Pulling all NAND tree input pins high
Driving low each NAND tree input pin sequentially per the NAND tree pin order
Checking the NAND tree output to ensure there is a toggle high-to-low or low-to-high for each NAND tree input
driven low
Table 5 lists the NAND tree pin order.
Pin Number
Pin Name
NAND Tree
Description
10
MDIO
Input
11
MDC
Input
12
RXD1
Input
13
RXD0
Input
15
CRS_DV
Input
16
REF_CLK
Input
17
RXER
Input
18
INTRP
Input
19
TXEN
Input
20
TXD0
Input
23
LED0
Input
21
TXD1
Output
Table 5. NAND Tree Test Pin Order – for KSZ8021/31RNL
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