參數(shù)資料
型號： KSZ8031RNLI
廠商： Micrel Inc
文件頁數(shù)： 43/43頁
文件大小： 0K
描述： TXRX PHY 10/100 3.3V 24-QFN
標(biāo)準(zhǔn)包裝： 75
類型： PHY 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： RMII
電源電壓： 1.8V，2.5V，3.3V
安裝類型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 24-QFN（4x4）
包裝： 管件
配用： 576-3862-ND - BOARD EVALUATION FOR KSZ8031RNL
其它名稱： 576-3788
Micrel, Inc.
KSZ8021RNL / KSZ8031RNL
August 2010
9
M9999-082710-1.0
Pin Description – KSZ8021RNL / KSZ8031RNL
Pin Number
Pin Name
Type
(1)
Pin Function
1
VDD_1.2
P
1.2V core VDD (power supplied by KSZ8021RNL / KSZ8031RNL)
Decouple with 2.2uF and 0.1uF capacitors-to-ground.
2
VDDA_3.3
P
3.3V analog VDD.
3
RXM
I/O
Physical receive or transmit signal (- differential)
4
RXP
I/O
Physical receive or transmit signal (+ differential)
5
TXM
I/O
Physical transmit or receive signal (- differential)
6
TXP
I/O
Physical transmit or receive signal (+ differential)
7
XO
O
Crystal feedback – for 25 MHz crystal
This pin is a no connect if oscillator or external clock source is used.
8
XI
I
RMII – 25MHz Mode:
25MHz +/-50ppm Crystal / Oscillator / External Clock Input
RMII – 50MHz Mode:
50MHz +/-50ppm Oscillator / External Clock Input
For unmanaged mode (power-up default setting),
KSZ8021RNL takes in the 50MHz clock on this pin.
KSZ8031RNL takes in the 25MHz crystal / clock on this pin.
After power-up, both the KSZ8021RNL and KSZ8031RNL can be programmed via
PHY register 1Fh bit [7] to either the 25MHz mode or 50MHz mode.
See also REF_CLK (pin 16) description.
9
REXT
I
Set physical transmit output current
Connect a 6.49K
Ω resistor-to-ground on this pin.
10
MDIO
I/O
Management Interface (MII) Data I/O
This pin has a weak pull-up, is open drain like, and requires an external 1.0K pull-
up resistor.
11
MDC
I
Management Interface (MII) Clock Input
This clock pin is synchronous to the MDIO data pin.
12
RXD1
Ipd/O
RMII Receive Data Output[1]
(2)
13
RXD0
Ipu/O
RMII Receive Data Output[0]
(2)
14
VDDIO
P
3.3V, 2.5V or 1.8V digital VDD
15
CRS_DV /
PHYAD[1:0]
Ipd/O
RMII Mode:
Carrier Sense/Receive Data Valid Output /
Config Mode:
The pull-up/pull-down value is latched as PHYAD[1:0] at the
de-assertion of reset. See “Strapping Options” section for details.
16
REF_CLK
Ipd/O
RMII – 25MHz Mode:
This pin provides the 50MHz RMII reference clock output to
the MAC.
RMII – 50MHz Mode:
This pin is a no connect.
For unmanaged mode (power-up default setting),
KSZ8021RNL is in RMII – 50MHz mode and does not use this pin.
KSZ8031RNL is in RMII – 25MHz mode and outputs the 50MHz RMII
reference clock on this pin.
After power-up, both KSZ8021RNL and KSZ8031RNL can be programmed via PHY
register 1Fh bit [7] to either 25MHz mode or 50MHz mode.
See also XI (pin 8) description.
17
RXER
Ipd/O
RMII Receive Error Output
18
INTRP
Ipu/Opu
Interrupt Output: Programmable Interrupt Output
This pin has a weak pull-up, is open drain like, and requires an external 1.0K pull-
up resistor.
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