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參數(shù)資料
| 型號(hào)： | KSZ8041MLL TR |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 18/65頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | TXRX 10/100 3.3V PHY MII 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類(lèi)型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | MII |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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Micrel, Inc.
KSZ8041TL/FTL/MLL
December 2009
25
M9999-120909-1.2
MII Management (MIIM) Interface
The KSZ8041TL/FTL/MLL supports the IEEE 802.3 MII Management Interface, also known as the Management Data
Input / Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the
KSZ8041TL/FTL/MLL. An external device with MIIM capability is used to read the PHY status and/or configure the PHY
settings. Further details on the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification.
The MIIM interface consists of the following:
x
A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
x
A specific protocol that operates across the aforementioned physical connection that allows a external controller
to communicate with one or more PHY devices. Each KSZ8041TL/FTL/MLL device is assigned a unique PHY
address between 1 and 7 by its PHYAD[2:0] strapping pins. Also, every KSZ8041TL/FTL/MLL device supports the
broadcast PHY address 0, as defined per the IEEE 802.3 Specification, which can be used to read/write to a
single KSZ8041TL/FTL/MLL device, or write to multiple KSZ8041TL/FTL/MLL devices simultaneously.
x
A set of 16-bit MDIO registers. Register [0:6] are required, and their functions are defined per the IEEE 802.3
Specification. The additional registers are provided for expanded functionality.
The following table shows the MII Management frame format for the KSZ8041TL/FTL/MLL.
Preamble
Start of
Frame
Read/Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0]
TA
Data
Bits [15:0]
Idle
Read
32 1’s
01
10
00AAA
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Z
Write
32 1’s
01
00AAA
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
Table 1. MII Management Frame Format
Interrupt (INTRP)
INTRP (pin 32) is an optional interrupt signal that is used to inform the external controller that there has been a status
update to the KSZ8041TL/FTL/MLL PHY register. Bits[15:8] of register 1Bh are the interrupt control bits, and are used to
enable and disable the conditions for asserting the INTRP signal. Bits[7:0] of register 1Bh are the interrupt status bits, and
are used to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading register
1Bh.
Bit 9 of register 1Fh sets the interrupt level to active high or active low.
MII Data Interface
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3 Specification. It provides a common
interface between physical layer and MAC layer devices, and has the following key characteristics:
x
Supports 10Mbps and 100Mbps data rates.
x
Uses a 25MHz reference clock, sourced by the PHY.
x
Provides independent 4-bit wide (nibble) transmit and receive data paths.
x
Contains two distinct groups of signals: one for transmission and the other for reception.
By default, the KSZ8041TL/FTL/MLL is configured to MII mode after it is power-up or reset with the following:
x
A 25MHz crystal connected to XI, XO (pins 15, 14), or an external 25MHz clock source (oscillator) connected to
XI.
x
CONFIGURATION[2:0] (pins 27, 41, 40) set to ‘000’ (default setting).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KSZ8041NLA3TR | TRANSCEIVER 10/100 32-MLF |
| KSZ8041NLJ TR | TXRX PHY 10/100 3.3V 32MLF |
| KSZ8041RNL | TXRX 10/100 3.3V PHY RMII 32-MLF |
| KSZ8041TLI TR | IC ETHERNET PHY IND 48TQFP |
| KSZ8051MLL TR | TXRX PHY 10/T100 3.3V MII 48LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8041MNLU | 制造商:MICREL 制造商全稱(chēng):Micrel Semiconductor 功能描述:10Base-T/100Base-TX Physical Layer Transceiver |
| KSZ8041MNLU TR | 功能描述:TXRX PHY 100BASE TX 3.3V 32QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):1/1 規(guī)程:RS422，RS485 電源電壓:4.75 V ~ 5.25 V 安裝類(lèi)型:通孔 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁(yè)面:1402 (CN2011-ZH PDF) |
| KSZ8041NL | 制造商:Micrel Inc 功能描述:10BASE-T/100BASE ETHERNET TRX SMD 制造商:Micrel Inc 功能描述:10BASE-T/100BASE ETHERNET TRX, SMD 制造商:Micrel Inc 功能描述:10BASE-T/100BASE ETHERNET TRX, SMD, Data Rate:100Mbps, Ethernet Type:IEEE 802.3u 制造商:Micrel Inc 功能描述:10BASE-T/100BASE ETHERNET TRX, SMD, Data Rate:100Mbps, Ethernet Type:IEEE 802.3u, Supply Voltage Max:3.3V, Digital IC Case Style:QFN, No. of Pins:32, IC Interface Type:MII, RMII, MSL:MSL 2 - 1 year, SVHC:No SVHC (19-Dec-2012), Base , RoHS Compliant: Yes |
| KSZ8041NL AM | 功能描述:以太網(wǎng) IC Physical Layer Transceiver 10/100BASE-T/TX (Lead Free) - Automotive Qualified RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8041NL AM TR | 功能描述:以太網(wǎng) IC Physical Layer Transceiver 10/100BASE-T/TX (Lead Free) - Automotive Qualified RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
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