參數(shù)資料
型號: KSZ8041MLL TR
廠商: Micrel Inc
文件頁數(shù): 8/65頁
文件大?。?/td> 0K
描述: TXRX 10/100 3.3V PHY MII 48LQFP
標(biāo)準(zhǔn)包裝: 1,000
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: MII
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 帶卷 (TR)
Micrel, Inc.
KSZ8041TL/FTL/MLL
December 2009
16
M9999-120909-1.2
Pin Number
Pin Name
Type
(1)
Pin Function
23
DUPLEX
Ipu/O
DUPLEX mode
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
During power-up / reset, this pin value is latched into register 0h bit 8 as the Duplex
Mode.
42
(KSZ8041TL)
NWAYEN
Ipu/O
Nway Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
During power-up / reset, this pin value is latched into register 0h bit 12.
If copper mode (FXEN=0), pin strap-in is Nway Auto-Negotiation Enable.
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
During power-up / reset, this pin value is latched into register 0h bit 12.
42
(KSZ8041FTL)
NWAYEN
Ipu/O
If fiber mode (FXEN=1), this pin configuration is always strapped to disable Auto-
Negotiation.
Note:
1. Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during
power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII/SMII signals to be latched high. In this
case, it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to
ISOLATE mode, or is not configured with an incorrect PHY Address.
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