參數(shù)資料
型號： KSZ8041MLL TR
廠商： Micrel Inc
文件頁數(shù)： 2/65頁
文件大?。?/td> 0K
描述： TXRX 10/100 3.3V PHY MII 48LQFP
標(biāo)準(zhǔn)包裝： 1,000
類型： 收發(fā)器
驅(qū)動器/接收器數(shù)： 1/1
規(guī)程： MII
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 帶卷 (TR)
Micrel, Inc.
KSZ8041TL/FTL/MLL
December 2009
10
M9999-120909-1.2
Pin Description- KSZ8041TL/FTL
Pin Number
Pin Name
Type
(1)
Pin Function
1
GND
Gnd
Ground
2
GND
Gnd
Ground
3
GND
Gnd
Ground
4
VDDA_1.8
P
1.8V analog VDD
5
VDDA_1.8
P
1.8V analog VDD
6
V1.8_OUT
P
1.8V output voltage from chip
7
VDDA_3.3
P
3.3V analog VDD
8
VDDA_3.3
P
3.3V analog VDD
9
RX-
I/O
Physical receive or transmit signal (- differential)
10
RX+
I/O
Physical receive or transmit signal (+ differential)
11
TX-
I/O
Physical transmit or receive signal (- differential)
12
TX+
I/O
Physical transmit or receive signal (+ differential)
13
GND
Gnd
Ground
14
XO
O
Crystal feedback
This pin is used only in MII mode when a 25MHz crystal is used.
This pin is a no connect if oscillator or external clock source is used, or if RMII
mode or SMII mode is selected.
15
XI /
REFCLK /
CLOCK
I
Crystal / Oscillator / External Clock Input
MII Mode:
25MHz +/-50ppm (crystal, oscillator, or external clock)
RMII Mode:
50MHz +/-50ppm (oscillator, or external clock only)
SMII Mode:
125MHz +/-100ppm (oscillator, or external clock only)
16
REXT
I/O
Set physical transmit output current
Connect a 6.49K
: resistor in parallel with a 100pF capacitor to ground on this
pin. See KSZ8041TL-FTL reference schematics.
17
GND
Gnd
Ground
18
MDIO
I/O
Management Interface (MII) Data I/O
This pin requires an external 4.7K
: pull-up resistor.
19
MDC
I
Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
20
RXD3 /
PHYAD0
Ipu/O
MII Mode:
Receive Data Output[3]
(2)
/
Config. Mode:
The pull-up/pull-down value is latched as PHYADDR[0] during
power-up / reset. See “Strapping Options” section for details.
21
RXD2 /
PHYAD1
Ipd/O
MII Mode:
Receive Data Output[2]
(2)
/
Config. Mode:
The pull-up/pull-down value is latched as PHYADDR[1] during
power-up / reset. See “Strapping Options” section for details.
22
RXD1 /
RXD[1] /
PHYAD2
Ipd/O
MII Mode:
Receive Data Output[1]
(2)
/
RMII Mode:
Receive Data Output[1]
(3)
/
Config. Mode:
The pull-up/pull-down value is latched as PHYADDR[2] during
power-up / reset. See “Strapping Options” section for details.
相關(guān)PDF資料
PDF描述
KSZ8041NLA3TR TRANSCEIVER 10/100 32-MLF
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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KSZ8041MNLU TR 功能描述:TXRX PHY 100BASE TX 3.3V 32QFN RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):1/1 規(guī)程:RS422，RS485 電源電壓:4.75 V ~ 5.25 V 安裝類型:通孔 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1402 (CN2011-ZH PDF)
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