參數(shù)資料
型號(hào): KSZ8051MNL-EVAL
廠商: Micrel Inc
文件頁數(shù): 10/59頁
文件大小: 0K
描述: BOARD EVALUATION FOR KSZ8051MNL
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng) PHY
嵌入式:
已用 IC / 零件: KSZ8051MNL
已供物品:
相關(guān)產(chǎn)品: 576-3845-ND - TXRX PHY 10/T100 3.3V 32QFN
576-3777-6-ND - TXRX PHY 10/T100 3.3V MII 32-QFN
576-3777-1-ND - TXRX PHY 10/T100 3.3V MII 32-QFN
576-3777-2-ND - TXRX PHY 10/T100 3.3V MII 32-QFN
576-3732-ND - TXRX PHY 10/T100 3.3V MII 32-QFN
其它名稱: 576-3865
Micrel, Inc.
KSZ8051MNL/RNL
July 2010
18
M9999-070910-1.0
Strapping Options – KSZ8051RNL
Pin Number
Pin Name
Type
(1)
Pin Function
15
14
13
PHYAD2
PHYAD1
PHYAD0
Ipd/O
Ipu/O
The PHY Address is latched at de-assertion of reset and is configurable to any value
from 0 to 7.
The default PHY Address is 00001.
PHY Address 00000 is enabled only if the B-CAST_OFF strapping pin is pulled high.
PHY Address bits [4:3] are set to ‘00’ by default.
18
29
28
CONFIG2
CONFIG1
CONFIG0
Ipd/O
The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.
CONFIG[2:0]
Mode
001
RMII
101
RMII Back-to-Back
000, 010 – 100, 110, 111
Reserved – not used
20
ISO
Ipd/O
ISOLATE mode
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into register 0h bit 10.
31
SPEED
Ipu/O
SPEED mode
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
At the de-assertion of reset, this pin value is latched into register 0h bit 13 as the
Speed Select, and also is latched into register 4h (Auto-Negotiation Advertisement)
as the Speed capability support.
16
DUPLEX
Ipu/O
DUPLEX mode
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
At the de-assertion of reset, this pin value is latched into register 0h bit 8.
30
NWAYEN
Ipu/O
Nway Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
At the de-assertion of reset, this pin value is latched into register 0h bit 12.
19
B-CAST_OFF
Ipd/O
Broadcast Off – for PHY Address 0
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY address
At the de-assertion of reset, this pin value is latched by the chip.
21
NAND_Tree#
Ipu/Opu
NAND Tree Mode
Pull-up (default) = Disable
Pull-down = Enable
At the de-assertion of reset, this pin value is latched by the chip.
Note:
1.
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin with internal pull-up (see Electrical
Characteristics for value) otherwise.
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive high/low during power-up or reset,
and consequently cause the PHY strap-in pins on the RMII signals to be latched to the unintended high/low states. In this case, external pull-ups (4.7K)
or pull-downs (1.0K) should be added on these PHY strap-in pins to ensure the intended values are strapped-in correctly.
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