KS8721B/BT Micrel, Inc. Strapping Options(Note 1) Pin Number Pi" />
參數(shù)資料
型號(hào)： KSZ8721BI TR
廠商： Micrel Inc
文件頁(yè)數(shù)： 32/32頁(yè)
文件大?。?/td> 0K
描述： TXRX PHY 10/100 2.3.3/5V 48-SSOP
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： MII，RMII
電源電壓： 2.375 V ~ 2.625 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 48-SSOP
包裝： 帶卷 (TR)
配用： 576-1627-ND - BOARD EVALUATION FOR KSZ8721BMC
576-1626-ND - BOARD EVALUATION FOR KSZ8721BL
其它名稱(chēng)： KSZ8721BITR
KSZ8721BITR-ND
March 2006
9
M9999-030106
KS8721B/BT
Micrel, Inc.
Strapping Options(Note 1)
Pin Number
Pin Name
Type(Note 2)
(Note 2)
Description
6,5,
PHYAD[4:1]/
Ipd/O
PHY Address latched at power-up/reset. The default PHY address is 00001.
4,3
RXD[0:3]
25
PHYAD0/
Ipu/O
INT#
9(3)
(3)
PCS_LPBK/
Ipd/O
Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
RXDV
11(3)
(3)
ISO/RXER
Ipd/O
Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
21(3)
(3)
RMII/COL
Ipd/O
Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
22(3)
(3)
RMII_BTB
Ipd/O
Enable RMII_BTB mode at power-up/reset. PD (default) = Disable, PU = Enable.
CRS
27
SPD100/
Ipu/O
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)
No FEF/
= 100Mbps. If SPD100 is asserted during power-up/reset, this pin also latched as
LED1
the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
means no Far_End _Fault.)
28
DUPLEX/
Ipu/O
Latched into Register 0h bit 8 during power-up/reset. PD = Half duplex, PU
LED2
(default) = Full duplex. If Duplex is pulled up during reset, this pin also latched as
the Duplex support in register 4h.
29
NWAYEN/
Ipu/O
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/
LED3
reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
30
PD#
Ipu
Power Down Enable. PU (default) = Normal operation, PD = Power down mode.
Note 1. Strap-in is latched during power-up or reset.
Note 2. Ipu = input w/ internal pull-up
Ipd = input w/ internal pull-down
Ipd/O = input w/ internal pull-down during reset, output pin otherwise
Ipu/O = input w/ internal pull-up during reset, output pin otherwise
PU = strap pin pull-up
PD = strap pin pull-down
Note 3. Some devices may drive MII pins that are designated as output (PHY) on power up, resulting in incorrect strapping values latched in at reset.
It is rcommended that an external pull down via 1kΩ resistor be used in these applications to augment the 8721's internal pull down.
6,5,
PHYAD[4:1]/
Ipd/O
PHY Address latched at power-up/reset. The default PHY address is 00001.
4,3
RXD[0:3]
25
PHYAD0/
Ipu/O
INT#
9
RXDV
11
21
22
CRS
27
SPD100/
Ipu/O
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)
No FEF/
= 100Mbps. If SPD100 is asserted during power-up/reset, this pin also latched as
LED1
the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
means no Far_End _Fault.)
28
DUPLEX/
Ipu/O
Latched into Register 0h bit 8 during power-up/reset. PD = Half duplex, PU
LED2
(default) = Full duplex. If Duplex is pulled up during reset, this pin also latched as
the Duplex support in register 4h.
29
NWAYEN/
Ipu/O
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/
LED3
reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
30
PD#
Ipu
Power Down Enable. PU (default) = Normal operation, PD = Power down mode.
Pin Number
Pin Name
Type
6,5,
PHYAD[4:1]/
Ipd/O
PHY Address latched at power-up/reset. The default PHY address is 00001.
4,3
RXD[0:3]
25
PHYAD0/
Ipu/O
INT#
PCS_LPBK/
Ipd/O
Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
RXDV
ISO/RXER
Ipd/O
Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
RMII/COL
Ipd/O
Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
RMII_BTB
Ipd/O
Enable RMII_BTB mode at power-up/reset. PD (default) = Disable, PU = Enable.
CRS
27
SPD100/
Ipu/O
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)
No FEF/
= 100Mbps. If SPD100 is asserted during power-up/reset, this pin also latched as
LED1
the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
means no Far_End _Fault.)
28
DUPLEX/
Ipu/O
Latched into Register 0h bit 8 during power-up/reset. PD = Half duplex, PU
LED2
(default) = Full duplex. If Duplex is pulled up during reset, this pin also latched as
the Duplex support in register 4h.
29
NWAYEN/
Ipu/O
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/
LED3
reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
30
PD#
Ipu
Power Down Enable. PU (default) = Normal operation, PD = Power down mode.
Pin Number
Pin Name
Type
6,5,
PHYAD[4:1]/
Ipd/O
PHY Address latched at power-up/reset. The default PHY address is 00001.
4,3
RXD[0:3]
25
PHYAD0/
Ipu/O
INT#
PCS_LPBK/
Ipd/O
Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
RXDV
ISO/RXER
Ipd/O
Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
RMII/COL
Ipd/O
Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
RMII_BTB
Ipd/O
Enable RMII_BTB mode at power-up/reset. PD (default) = Disable, PU = Enable.
27
SPD100/
Ipu/O
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)
No FEF/
= 100Mbps. If SPD100 is asserted during power-up/reset, this pin also latched as
LED1
the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
means no Far_End _Fault.)
28
DUPLEX/
Ipu/O
Latched into Register 0h bit 8 during power-up/reset. PD = Half duplex, PU
LED2
(default) = Full duplex. If Duplex is pulled up during reset, this pin also latched as
the Duplex support in register 4h.
29
NWAYEN/
Ipu/O
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/
LED3
reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
30
PD#
Ipu
Power Down Enable. PU (default) = Normal operation, PD = Power down mode.
Description
6,5,
PHYAD[4:1]/
Ipd/O
PHY Address latched at power-up/reset. The default PHY address is 00001.
4,3
RXD[0:3]
PCS_LPBK/
Ipd/O
Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
RXDV
ISO/RXER
Ipd/O
Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
RMII/COL
Ipd/O
Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
RMII_BTB
Ipd/O
Enable RMII_BTB mode at power-up/reset. PD (default) = Disable, PU = Enable.
27
SPD100/
Ipu/O
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)
No FEF/
= 100Mbps. If SPD100 is asserted during power-up/reset, this pin also latched as
LED1
the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
means no Far_End _Fault.)
28
DUPLEX/
Ipu/O
Latched into Register 0h bit 8 during power-up/reset. PD = Half duplex, PU
LED2
(default) = Full duplex. If Duplex is pulled up during reset, this pin also latched as
the Duplex support in register 4h.
29
NWAYEN/
Ipu/O
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/
LED3
reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
30
PD#
Ipu
Power Down Enable. PU (default) = Normal operation, PD = Power down mode.
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