Micrel, Inc. M9999-030106 14 March 2006 Transmit Data [1:0] (TXD[1:0]) Transmit Data TXD[1:0] shall transition synchronously wit" />
參數(shù)資料
型號(hào)： KSZ8721BI TR
廠商： Micrel Inc
文件頁數(shù)： 6/32頁
文件大?。?/td> 0K
描述： TXRX PHY 10/100 2.3.3/5V 48-SSOP
標(biāo)準(zhǔn)包裝： 1,000
類型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： MII，RMII
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 48-SSOP
包裝： 帶卷 (TR)
配用： 576-1627-ND - BOARD EVALUATION FOR KSZ8721BMC
576-1626-ND - BOARD EVALUATION FOR KSZ8721BL
其它名稱： KSZ8721BITR
KSZ8721BITR-ND
KS8721B/BT
Micrel, Inc.
M9999-030106
14
March 2006
Transmit Data [1:0] (TXD[1:0])
Transmit Data TXD[1:0] shall transition synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are
accepted for transmission by the PHY. TXD[1:0] shall be “00” to indicate idle when TX_EN is de-asserted. Values of TXD[1:0]
other than “00” when TX_EN is de-asserted are reserved for out-of-band signalling (to be dened). Values other than “00”
on TXD[1:0] while TX_EN is deasserted shall be ignored by the PHY.
Collision Detection
Since the denition of CRS_DV and TX_EN both contain an accurate indication of the start of frame, the MAC can reliably
regenerate the COL signal of the MII by ANDing TX_EN and CRS_DV.
During the IPG time following the successful transmission of a frame, the COL signal is asserted by some transceivers as a
self-test. The Signal Quality Error (SQE) function will not be supported by the reduced MII due to the lack of the COL signal.
Historically, SQE was present to indicate that a transceiver located physically remote from the MAC was functioning. Since
the reduced MII only supports chip-to-chip connections on a PCB, SQE functionality is not required.
RX_ER
The PHY shall provide RX_ER as an output according to the rules specied in IEEE 802.3u [2] (see Clause 24, Figure 24-
11 - Receive State Diagram). RX_ER shall be asserted for one or more REF_CLK periods to indicate that an error (e.g. a
coding error or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sublayer)
was detected somewhere in the frame presently being transferred from the PHY. RX_ER shall transition synchronously with
respect to REF_CLK. While CRS_DV is de-asserted, RX_ER shall have no effect on the MAC.
RMII AC Characteristics
Symbol Parameter
Min
Typ
Max
Units
REF_CLK Frequency
50
MHz
REF_CLK Duty Cycle
35
65
%
tSU
TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, RX_ER Data Set-Up to REF_CLK Rising
4
ns
tH
TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, RXER Data Hold from REF_CLK
2
ns
Rising Edge
RMII Transmit Timing
REF_CLK
20ns
tod
RXD[1:0]
RXDV
RXER
Parameter
Min
Typ
Max
Units
REF_CLK Frequency
50
MHz
TXEN, TXD[1:0], TX_EN, Data Setup to REF_CLK rising edge
4
ns
TXEN, TXD[1:0], TX_EN, Data hold from REF_CLK rising edge
2
ns
Symbol Parameter
Min
Typ
Max
Units
REF_CLK Frequency
50
MHz
REF_CLK Duty Cycle
35
65
%
TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, RX_ER Data Set-Up to REF_CLK Rising
4
ns
TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, RXER Data Hold from REF_CLK
2
ns
Rising Edge
Symbol Parameter
Min
Typ
Max
Units
REF_CLK Frequency
50
MHz
REF_CLK Duty Cycle
35
65
%
TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, RX_ER Data Set-Up to REF_CLK Rising
4
ns
TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, RXER Data Hold from REF_CLK
2
ns
Symbol Parameter
Min
Typ
Max
Units
REF_CLK Frequency
50
MHz
REF_CLK Duty Cycle
35
65
%
TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, RX_ER Data Set-Up to REF_CLK Rising
4
ns
TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, RXER Data Hold from REF_CLK
2
ns
Symbol Parameter
Min
Typ
Max
Units
REF_CLK Frequency
50
MHz
REF_CLK Duty Cycle
35
65
%
TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, RX_ER Data Set-Up to REF_CLK Rising
4
ns
TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, RXER Data Hold from REF_CLK
2
ns
REF_CLK Frequency
50
MHz
REF_CLK Duty Cycle
35
65
%
t
Rising Edge
Symbol Parameter
Min
Typ
Max
Units
REF_CLK Frequency
50
MHz
REF_CLK Duty Cycle
35
65
%
TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, RX_ER Data Set-Up to REF_CLK Rising
4
ns
TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, RXER Data Hold from REF_CLK
2
ns
Parameter
Min
Typ
Max
Units
REF_CLK Frequency
50
MHz
TXEN, TXD[1:0], TX_EN, Data Setup to REF_CLK rising edge
4
ns
TXEN, TXD[1:0], TX_EN, Data hold from REF_CLK rising edge
2
ns
Parameter
Min
Typ
Max
Units
REF_CLK Frequency
50
MHz
TXEN, TXD[1:0], TX_EN, Data Setup to REF_CLK rising edge
4
ns
TXEN, TXD[1:0], TX_EN, Data hold from REF_CLK rising edge
2
ns
Parameter
Min
Typ
Max
Units
REF_CLK Frequency
50
MHz
TXEN, TXD[1:0], TX_EN, Data Setup to REF_CLK rising edge
4
ns
TXEN, TXD[1:0], TX_EN, Data hold from REF_CLK rising edge
2
ns
REF_CLK Frequency
50
MHz
TXEN, TXD[1:0], TX_EN, Data Setup to REF_CLK rising edge
4
ns
TXEN, TXD[1:0], TX_EN, Data hold from REF_CLK rising edge
2
ns
Parameter
Min
Typ
Max
Units
REF_CLK Frequency
50
MHz
TXEN, TXD[1:0], TX_EN, Data Setup to REF_CLK rising edge
4
ns
TXEN, TXD[1:0], TX_EN, Data hold from REF_CLK rising edge
2
ns
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