參數(shù)資料
型號(hào)： KSZ8721BLI TR
廠商： Micrel Inc
文件頁(yè)數(shù)： 34/35頁(yè)
文件大小： 0K
描述： TXRX PHY 10/100 2.3.3/5V 48-LQFP
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： MII，RMII
電源電壓： 3 V ~ 3.6 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
配用： 576-1627-ND - BOARD EVALUATION FOR KSZ8721BMC
576-1626-ND - BOARD EVALUATION FOR KSZ8721BL
其它名稱(chēng)： KSZ8721BLITR
KSZ8721BLITR-ND
Micrel, Inc.
KS8721BL/SL
June 2009
8
M9999-062509-1.3
Pin Number
Pin Name
Type
(1)
Pin Function
24
VDDIO
P
Digital IO 2.5/3.3V tolerant power supply. 3.3V power input of voltage regulator.
See “Circuit Design Ref. for Power Supply” section for details.
25
INT#/
PHYAD0
Ipu/O
Management Interface (MII) Interrupt Out. Interrupt level set by Register 1f, bit 9.
During reset, latched as PHYAD[0]. See “Strapping Options” section for details.
26
LED0/
TEST
Ipu/O
Link/Activity LED Output. The external pull-down enable test mode and only used for
the factory test. Active low.
Link/Act
Pin State
LED Definition PHYAD0
No Link
H
“Off”
Link
L
“On”
Act
–
“Toggle”
27
LED1/
SPD100/
nFEF
Ipu/O
Speed LED Output. Latched as SPEED (Register 0, bit 13) during power-up/ reset. See
“Strapping Options” section for details. Active low.
Speed
Pin State
LED Definition
10BT
H
“Off”
100BT
L
“On”
28
LED2
Ipu/O
Full-duplex LED Output. Latched as DUPLEX (register 0h, bit 8) during power-up/ reset.
See “Strapping DUPLEX Options” section for details. Active low.
Duplex
Pin State
LED Definition
Half
H
“Off”
Full
L
“On”
29
LED3/
NWAYEN
Ipu/O
Collision LED Output. Latched as ANEG_EN (register 0h, bit 12) during power-up/
reset. See “Strapping Options” section for details.
Collision
Pin State
LED Definition
No Collision
H
“Off”
Collision
L
“On”
30
PD#
Ipu
Power Down. 1 = Normal operation, 0 = Power-down. Active low.
31
VDDRX
P
Analog 2.5V power supply. See “Circuit Design Ref. for Power Supply” section for
details.
32
RX-
I
Receive Input. Differential receive input pins for 100FX, 100BASE-TX, or 10BASE-T.
33
RX+
I
Receive Input: Differential receive input pin for 100FX, 100BASE-TX, or 10BASE-T.
34
FXSD/
FXEN
Ipd/O
Fiber Mode Enable / Signal Detect in Fiber Mode. If FXEN = 0, FX mode is disable. The
default is “0”. See “100BT FX Mode” section for more details.
35
GND
Gnd
Ground.
36
GND
Gnd
Ground.
37
REXT
I
External resistor (6.49kW ) connects to REXT and GND.
38
VDDRCV
P
Analog 2.5V power supply. 2.5V power output of voltage regulator. See “Circuit Design
Ref. for Power Supply” section for details.
39
GND
Gnd
Ground.
40
TX-
O
Transmit Outputs: Differential transmit output for 100FX, 100BASE-TX, or 10BASE-T.
41
TX+
O
Transmit Outputs: Differential transmit output for 100FX, 100BASE-TX, or 10BASE-T.
42
VDDTX
P
Transmitter 2.5V power supply. See “Circuit Design Ref. for Power Supply” section for
details.
43
GND
Gnd
Ground.
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