參數(shù)資料
型號： KSZ8841-16MBLI
廠商： Micrel Inc
文件頁數(shù)： 57/105頁
文件大小： 0K
描述： IC MAC CTRLR 8/16BIT 100-LBGA
標(biāo)準(zhǔn)包裝： 260
控制器類型： 以太網(wǎng)控制器，MAC
接口： 總線
電源電壓： 3.1 V ~ 3.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LBGA
供應(yīng)商設(shè)備封裝： 100-LFBGA
包裝： 散裝
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
October 2007
55
M9999-102207-1.6
Bank 3 On-Chip Bus Control Register (0x00): OBCR
This register controls the on-chip bus speed for the KSZ8841M. It is used for power management when the external host
CPU is running at a slow frequency. The default of the on-chip bus speed is 125 MHz without EEPROM. When the
external host CPU is running at a higher clock rate, the on-chip bus should be adjusted for the best performance.
Bit
Default Value
R/W
Description
15-2
-
RO
Reserved.
1-0
0x0
RW
OBSC On-Chip Bus Speed Control
00: 125MHz.
01: 62.5MHz.
10: 41.66MHz.
11: 25MHz.
Note: When external EEPROM is enabled, the bit 1 in Configparm word (0x6H) is used to
contol this speed as below:
Bit 1 = 0 , this value will be 00 for 125 MHz.
Bit 1 = 1 , this value will be 11 for 25 MHz.
(User still can write these two bits to change speed after EEPROM data loaded)
Bank 3 EEPROM Control Register (0x02): EEPCR
To support an external EEPROM, tie the EEPROM Enable (EEEN) pin to High; otherwise, tie it to Low. If an external
EEPROM is not used, the default chip Base Address (0x300), and the software programs the host MAC address. If an
EEPROM is used in the design (EEPROM Enable pin to High), the chip Base Address and host MAC address are loaded
from the EEPROM immediately after reset. The KSZ8841M allows the software to access (read and write) the EEPROM
directly; that is, the EEPROM access timing can be fully controlled by the software if the EEPROM Software Access bit is
set.
Bit
Default Value
R/W
Description
15-5
-
RO
Reserved.
4
0
RW
EESA EEPROM Software Access
1: enable software to access EEPROM through bit 3 to bit 0.
0: disable software to access EEPROM.
3
-
RO
EECB EEPROM Status Bit
Data Receive from EEPROM. This bit directly reads the EEDI pin.
2-0
0x0
RW
EECB EEPROM Control Bits
Bit 2: Data Transmit to EEPROM. This bit directly controls the device’s EEDO pin.
Bit 1: Serial Clock. This bit directly controls the device’s EESK pin.
Bit 0: Chip Select for EEPROM. This bit directly controls the device’s EECS pin.
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