參數(shù)資料
型號(hào): KSZ8841-16MBLI
廠(chǎng)商: Micrel Inc
文件頁(yè)數(shù): 91/105頁(yè)
文件大?。?/td> 0K
描述: IC MAC CTRLR 8/16BIT 100-LBGA
標(biāo)準(zhǔn)包裝: 260
控制器類(lèi)型: 以太網(wǎng)控制器,MAC
接口: 總線(xiàn)
電源電壓: 3.1 V ~ 3.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 100-LBGA
供應(yīng)商設(shè)備封裝: 100-LFBGA
包裝: 散裝
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
October 2007
86
M9999-102207-1.6
Offset
Counter Name
Description
0x19
TxMulticastPkts
Tx good multicast packets (not including error multicast packets or valid broadcast packets)
0x1A
TxUnicastPkts
Tx good unicast packets
0x1B
TxDeferred
Tx packets by a port for which the 1st Tx attempt is delayed due to the busy medium
0x1C
TxTotalCollision
Tx total collision, half duplex only
0x1D
TxExcessiveCollision
A count of frames for which Tx fails due to excessive collisions
0x1E
TxSingleCollision
Successfully Tx frames on a port for which Tx is inhibited by exactly one collision
0x1F
TxMultipleCollision
Successfully Tx frames on a port for which Tx is inhibited by more than one collision
Table 12. Port 1 MIB Counters Indirect Memory Offsets
Example:
1. MIB Counter Read (read port 1 “Rx64Octets” counter at indirect address offset 0x0E)
Write to reg. IACR with 0x1C0E (set indirect address and trigger a read MIB counters operation)
Then
Read reg. IADR5 (MIB counter value 31-16) // If bit 31 = 1, there was a counter overflow
// If bit 30 = 0, restart (re-read) from this register
Read reg. IADR4 (MIB counter value 15-0)
Additional MIB Information
In the heaviest condition, the byte counter will overflow in 2 minutes. It is recommended that the software read all
the counters at least every 30 seconds.
MIB counters are designed as “read clear”. That is, these counters will be cleared after they are read.
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