參數(shù)資料
型號： KSZ8841-16MBLI
廠商： Micrel Inc
文件頁數(shù)： 68/105頁
文件大?。?/td> 0K
描述： IC MAC CTRLR 8/16BIT 100-LBGA
標(biāo)準(zhǔn)包裝： 260
控制器類型： 以太網(wǎng)控制器，MAC
接口： 總線
電源電壓： 3.1 V ~ 3.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LBGA
供應(yīng)商設(shè)備封裝： 100-LFBGA
包裝： 散裝
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
October 2007
65
M9999-102207-1.6
Bank 16 RXQ Memory Information Register (0x0A): RXMIR
This register indicates the amount of receive data available in the RXQ of the QMU module.
Bit
Default Value
R/W
Description
15-13
-
RO
Reserved.
12-0
-
RO
RXMA Receive Packet Data Available
The amount of Receive packet data available is represented in units of byte. The RXQ
memory is used for both frame payload, status word. There is total 4096 bytes in RXQ. This
counter will update after a complete packet is received and also issues an interrupt when
receive interrupt enable IER[13] in Bank 18 is set.
Note: Software must be written to empty the RXQ memory to allow for the new RX frame. If
this is not done, the frame may be discarded as a result of insufficient RXQ memory.
Bank 17 TXQ Command Register (0x00): TXQCR
This register is programmed by the Host CPU to issue a transmit command to the TXQ. The present transmit frame in
the TXQ memory is queued for transmit.
Bit
Default Value
R/W
Description
15-1
-
RO
Reserved
0
0x0
RW
TXETF Enqueue TX Frame
When this bit is written as 1, the current TX frame prepared in the TX buffer is queued for
transmit.
Note: This bit is self-clearing after the frame is finished transmitting. The software should wait
for the bit to be cleared before setting up another new TX frame.
Bank 17 RXQ Command Register (0x02): RXQCR
This register is programmed by the Host CPU to issue release command to the RXQ. The current frame in the RXQ
frame buffer is read only by the host and the memory space is released.
Bit
Default Value
R/W
Description
15-1
-
RO
Reserved.
0
0x0
RW
RXRRF Release RX Frame
When this bit is written as 1, the current RX frame buffer is released.
Note: This bit is self-clearing after the frame memory is released. The software should wait for
the bit to be cleared before processing new RX frame.
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