參數(shù)資料
型號(hào): KSZ8841-16MQL A6
廠商: Micrel Inc
文件頁(yè)數(shù): 15/105頁(yè)
文件大小: 0K
描述: IC MAC CTRLR 8/16BIT 128-PQFP
標(biāo)準(zhǔn)包裝: 66
控制器類(lèi)型: 以太網(wǎng)控制器,MAC
接口: 總線
電源電壓: 3.1 V ~ 3.5 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤(pán)
配用: 576-1631-ND - BOARD EVALUATION KSZ8841-16MQL
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
October 2007
17
M9999-102207-1.6
Ball Description for KSZ8841-16 Chip (8/16-Bit)
Ball Number
Ball Name
Type
Ball Function
E8
TEST_EN
I
Test Enable
For normal operation, pull-down this ball to ground.
D10
SCAN_EN
I
Scan Test Scan Mux Enable
For normal operation, pull-down this ball to ground.
A10
P1LED2
Opu
B10
P1LED1
Opu
C10
P1LED0
Opu
Port 1 LED indicators
1 defined as follows:
Switch Global Control Register 5:
SGCR5 bit [15,9]
[0,0] Default
[0,1]
P1LED3
2
P1LED2
Link/Act
100Link/Act
P1LED1
Full duplex/Col
10Link/Act
P1LED0
Speed
Full duplex
Reg. SGCR5 bit [15,9]
[1,0]
[1,1]
P1LED3
2
Act
P1LED2
Link
P1LED1
Full duplex/Col
P1LED0
Speed
Notes:
1. Link = On; Activity = Blink; Link/Act = On/Blink; Full Dup/Col = On/Blink;
Full Duplex = On (Full duplex); Off (Half duplex)
Speed = On (100BASE-T); Off (10BASE-T)
2. P1LED3 is ball A4.
D9
RDYRTNN
Ipd
Ready Return Not:
For VLBus-like mode: Asserted by the host to complete synchronous read
cycles. If the host doesn’t connect to this ball, assert this ball.
A8
BCLK
Ipd
Bus Interface Clock
Local bus clock for synchronous bus systems. Maximum frequency is 50MHz.
This ball should be tied Low or unconnected if it is in asynchronous mode.
D8
PMEN
Opu
Power Management Event Not
When asserted (Low), this signal indicates that a power management event has
occurred in the system when a wake-up signal is detected by KSZ8841M.
B8
SRDYN
Opu
Synchronous Ready Not
Ready signal to interface with synchronous bus for both EISA-like and VLBus-
like extend accesses.
For VLBus-like mode, the falling edge of this signal indicates ready. This signal
is synchronous to the bus clock signal BCLK.
C8
INTRN
Opd
Interrupt
Active Low signal to host CPU to indicate an interrupt status bit is set, this ball
need an external 4.7K pull-up resistor.
A7
LDEVN
Opd
Local Device Not
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